TSM
Taiwan Semiconductor Manufacturing
- Conviction
- 5 / 5
- Sizing
- Large · concentrated
- Horizon
- 18–36 months
- Entry
- 30% reserved · 232
The structurally cleanest long in the cohort: a wide-and-strengthening leading-edge logic monopoly (~71% pure-foundry, ~85–90% sub-5nm, HHI ~7,500–8,200) compounded by a packaging chokepoint (CoWoS-L) where NVIDIA alone has booked >50% of capacity through 2027. Six of seven analysts rated 4–5 conviction; the consistent "weakest" reads all converge on the same root cause — multiple full, chokepoint real, Taiwan tail uninsurable — which is precisely the framing that justifies a concentrated position. The single thing that breaks it is non-competitive and non-financial.
Asymmetry · ~1.75 : 1 modal · ~3 : 1 on a drawdown.
This is a position you take for the chokepoint, not the multiple. A 25% drawdown shifts asymmetry to ~3:1 and conviction goes from 5 to "back up the truck." Pair-trade overlay: TSM long / INTC short to express foundry leadership as a relative-value position.
Competitive position · the river flows one way.
competitor.md Phase 3Cost & switching are both 5s.
70% revenue share funds capex no one can match. Apple's pre-payment cycle uniquely funds TSMC's capital cycle. The Qualcomm 2022 episode (8 Gen 1 → 8+ Gen 1) is the canonical demonstration: when a fabless customer flees a foundry, they flee to TSMC, never the other way.
Efficient scale is also 5.
A leading-edge fab is now $20–30B+ of capex with a 4–6 year payback that requires running near-100% utilization at the leading node. The economic geometry only supports one or two viable players globally. Samsung and Intel are demonstrating in real time how unviable the second seat is.
Intangibles 5: brand + regulatory.
90%+ of leading-edge AI logic transistors. Deeply embedded in CHIPS Act, METI Kumamoto subsidies, EU programs. Effectively a national-security-tier supplier for the US, Japan, and increasingly Germany.
Supply chain · symmetric across competitors.
Every ZEISS / ASML / Japanese-resist event hurts Samsung and Intel identically; TSMC's relative position improves in every cross-vendor stress. The April 2026 M7.7 Japan quake shutting TOK Koriyama (~25% of global advanced resist) for 4–8 weeks is a live in-cohort stress test.
flowchart LR classDef sev fill:oklch(32% 0.10 28),stroke:oklch(60% 0.14 28),color:oklch(95% 0.05 28),font-family:'Geist Mono',font-size:11px classDef elev fill:oklch(35% 0.10 95),stroke:oklch(72% 0.13 95),color:oklch(95% 0.04 95),font-family:'Geist Mono',font-size:11px classDef ok fill:oklch(28% 0.06 230),stroke:oklch(58% 0.08 230),color:oklch(94% 0.04 230),font-family:'Geist Mono',font-size:11px classDef anchor fill:oklch(40% 0.13 95),stroke:oklch(80% 0.13 95),color:oklch(98% 0.05 95),font-family:'Geist Mono',font-weight:600,font-size:13px ASML[ASML EUV / High-NA
sole-source · NL]:::sev ZEISS[ZEISS Oberkochen
optics · sole]:::sev INPRIA[Inpria High-NA resist
Corvallis · sole]:::sev KLA[KLA inspection · sole]:::elev TEL[Tokyo Electron
coater-developer]:::elev BESI[BESI hybrid bonding]:::elev TOK[TOK Koriyama resist
Apr 2026 quake]:::sev AJI[Ajinomoto ABF · sole]:::elev GAS[Linde · Air Liquide
de-risked post-2022]:::ok SHIN[Shin-Etsu / SUMCO
~60% 300mm wafers]:::elev TSM{{TSMC
Hsinchu · Tainan · Kaohsiung
+ Arizona · Kumamoto · Dresden}}:::anchor COWOS[CoWoS-L packaging
35K → 130K WPM]:::elev AAPL[Apple ~25%
pre-pays per node]:::ok NVDA[NVIDIA ~22-25%
510K CoWoS-L slots]:::ok AMD[AMD]:::ok AVGO[Broadcom ~15% CoWoS]:::ok QCOM[Qualcomm]:::ok MTK[MediaTek]:::ok HYP[Hyperscaler ASIC
TPU · MTIA · Maia · OpenAI]:::ok ZEISS --> ASML ASML --> TSM INPRIA --> ASML KLA --> TSM TEL --> TSM BESI --> COWOS TOK --> TSM AJI --> COWOS GAS --> TSM SHIN --> TSM TSM --> COWOS TSM --> AAPL TSM --> NVDA TSM --> AMD COWOS --> NVDA COWOS --> AVGO TSM --> QCOM TSM --> MTK COWOS --> HYP
ZEISS Oberkochen optics — sole-source for every EUV scanner globally. Single-facility single-point-of-failure. But the impact is symmetric — it hurts every leading-edge fab equally.
2 = strong. The strongest pass-through profile in the cohort outside ASML itself. Q1 2026 GM 66.2% (vs guide 63–65%); long-term GM target raised to 56%+; 5–10% advanced-node hikes for four consecutive years 2026–2029.
Doubling from 35K. NVIDIA ~60%, Broadcom ~15%, AMD ~11%. >85% pre-allocated. Not a demand call — a booking schedule.
Customer & end-market.
Customer-funded capex. Apple pre-pays per node; NVIDIA had to lock 800K+ wafers and 510K CoWoS-L slots through 2027 just to secure supply. Reservation deposits are non-refundable. The customer base finances the supplier's growth — concentration as leverage, not risk.
Catalyst calendar.
Kill criteria.
- Samsung SF2P yields hold at 70%+ for two consecutive quarters AND Qualcomm or AMD announces a >20% volume shift to Samsung 2nm by H2 2026. Breaks the customer-flight-is-one-directional axiom.
- TSMC FY26 gross margin compresses below 56% in any single quarter outside an Arizona-dilution explanation. The whole financial case rests on the 56%+ structural floor.
- Section 232 lands as a broad tariff without Arizona/anchor-customer exemption AND Q3-Q4 2026 prints show <50% pass-through. Modal outcome is priced; punitive outcome with weak pass-through breaks the "pricing power absorbs everything" premise.
- Cross-strait posture escalates to declared blockade exercise or kinetic-precursor mobilization signal validated by USINDOPACOM-grade public statements. Position is closed regardless of conviction; portfolio-protection trigger.
- CoWoS-L capacity ramp slips by >25% on the 2026 exit (target ~130K WPM; floor ~98K WPM). The packaging chokepoint is the compounding leg of the moat.
- TSMC's reverse DCF requires >18% 10-year revenue CAGR to justify the price (vs current 13–15%). Either a meaningful price run with no earnings revision or a 2027 capex pause that compresses the forward growth path. Asymmetry breaks.
"This is a position you take for the chokepoint, not the multiple."— PM thesis · TSM · asymmetry verdict