Semiconductor Industry + AI Power Infrastructure — Domain Synthesis

§ 010. Cohort Scope Decision (2026-05-04 Refresh + C-COHERENCE Update)

This cohort formally extends past pure semiconductors to include AI power-infrastructure names. Two of the four added deep-dive tickers — ETN (Eaton) and VRT (Vertiv) — are not semiconductor companies. They belong in this cohort because the unifying analytical frame in the user's notes is the chip-to-grid value chain, not "semis." Every relevant note treats the voltage path from the substation, through the building, into the rack, onto the board, and into the die as a single continuous system. "Every layer of the voltage stack is being redesigned simultaneously" (per "The AI Power Crisis — Part 1"). "This is not a story about a single chip winning. It is a story about an entire value chain moving" (per "The AI Power Crisis — Part 2").

C-COHERENCE insight — cohort architecture: The cohort holds chip-layer names (NVTS/TXN) and grid/system-layer names (ETN/VRT) as independent positions, not as a chain. Per Finding 12 (C-VRT-1 fan-out, refinement-log), NVIDIA GTC March 2026 named VRT/ETN/Schneider all at the systems tier, and TI exclusively at the silicon-anchor tier — but no box-builder names a power-semi partner by commercial design. ETN customer-analyst confirmed: Eaton stays vendor-agnostic on power-semi supplier (per Finding 6, ETN thesis). The chip-to-grid frame justifies why we research these names together, not because their P&Ls flow mechanically through each other. The downstream D4 adjacency rationale must be explicit on this.

Cohort portfolio architecture (finalized by C-COHERENCE pass):

• Long, high conviction (core): NVDA, TSM, AVGO, TXN
• Long, medium conviction (completion): ETN (buy on weakness, 2.0–2.5% NAV), VRT (probe due to valuation, 1.0–1.5% NAV)
• Long, probe (architectural bet): NVTS (0.5–0.75% NAV)
• Short, high conviction: WOLF (structural SiC break), INTC (foundry-leadership binary)
• Portfolio-construction constraint: Combined ETN+VRT ≤ 1.5–2.0x TXN NAV position. If TXN is 3% NAV, ETN+VRT combined cannot exceed 4.5–6.0% NAV. This is a non-negotiable concentration discipline rule (per Finding 16, refinement-log).

The expansion is the deferred next step: the prior portfolio summary's Open Question §4 explicitly flagged "Vertiv / Schneider / Eaton / Delta Electronics" as the next mini-cohort to run. Vertiv Q4'25 organic orders +152% YoY, $15B backlog, 2.9x book-to-bill (per "The AI Power Crisis — Part 2") made the case time-bound rather than thematic.

A note on honesty: corpus support is strongest for VRT and NVTS/TXN on strategic specificity, and thinnest for ETN. ETN appears only twice in the corpus before the analyst expansion — once for Q4'25 +3x YoY DC order growth, once as a supercapacitor manufacturer. The downstream ETN deep-dive (completed 2026-05-04) leaned on primary research and Boyd Thermal ($9.5B, closed March 2026) was the single most consequential structural development not in the vault.

§ 021. Executive Summary

The corpus is unified around a single, structurally simple thesis: AI compute is one continuous voltage system, from the power plant to the transistor, and every layer of that system is being redesigned simultaneously. The user treats the delivery problem of energy to compute as the binding question of the next decade. "The bottleneck is shifting from how much electricity we can generate to how little we lose and how reliably we can push it all the way to the transistor" (per "The AI Power Crisis — Part 1"). "The rack is becoming the new grid" (per "The AI Power Crisis — Part 2").

Three theses run through every note. First, the voltage stack is being rebuilt at every layer simultaneously — HVDC at the grid, 800V DC at the building, the transition from 48V to 800V at the rack, GaN/SiC replacing silicon in conversion, and BSPDN at the die. Second, the supply chain — not the technology — chose 800V. The EV industry spent 5–7 years building a mature 1200V SiC / 650V GaN ecosystem; AI infrastructure inherits it. As TI's Jeffrey Morroni is quoted: "the technology and semiconductor infrastructure that safely supports an 800V EV looks very similar to what an 800V rack infrastructure needs" (per "The AI Power Crisis — Part 2"). Automotive softness is a tailwind for power-semi vendors: AI infrastructure is the new demand curve absorbing the supply EVs already built. Third, the SemiAnalysis three-bottleneck frame organizes everything: logic (TSMC wafers), memory (HBM), and power (the grid plus the building plus the rack plus the die). Every news story is one bottleneck in disguise.

The user's strongest convictions are picks-and-shovels positions where the bottleneck math is durable: TSMC, ASML, SK Hynix, Broadcom, Nvidia at the silicon end; Vertiv, Eaton, Schneider, Delta at the box-builder end; Infineon, TI, Navitas in between as the GaN/SiC conversion layer. The user is openly skeptical of Intel's foundry path. Wolfspeed is the only name carrying a clearly bearish framing — explicitly flagged as proof that "structural transitions do not guarantee equal outcomes."

The user is not a near-term valuation buyer. Note 1 explicitly separates the demand call from the valuation call. This synthesis represents conviction on direction and structural position, not on entry points. Entry-point discipline per ticker is in the individual thesis files.

The deepest cross-cutting theme is the unit cost of intelligence: cost per token has fallen 2–4x per generation. Cheaper intelligence does not slow capex; it pulls in more applications. The user is bullish on the entire chip-to-grid stack because they are bullish on this denominator continuing to compress.

§ 032. The Value Chain — Chip-to-Grid Stack

The stack runs end-to-end from the power plant down to ~0.7V at the transistor. This section leads with the chip-to-grid voltage path. Upper layers are power-and-thermal infrastructure (ETN, VRT, Schneider, Delta). Middle layers are the 800V transition machinery (NVTS, TXN, Infineon, onsemi, Vicor, MPWR). Lower layers are the chip stack (NVDA, TSM, AVGO, INTC, memory, WFE, EDA, materials).

C-COHERENCE addition — $/MW asymmetry (Findings 8 + 11): G1-G4 captures $700K–$2.8M per MW of AI-DC build (ETN $500K–$1.1M today → $1.0–2.0M Kyber era; VRT $600K–$1.3M today → $1.2–2.8M Kyber era). This is 20–60x larger than the power-semi BOM at L8b/L8c per MW. The chip-to-grid value chain's dollar-weighted center of mass sits at G1-G4 (electrical infrastructure), not at L8b/L8c (power semis). Power semis are higher growth in % terms; power infrastructure is the dollar-volume layer of the AI-DC build. This is the strongest structural argument for the cohort scope expansion — ETN/VRT capture the money, not just the narrative.

C-COHERENCE addition — cooling/thermal as a load-bearing layer (Findings 6 + 14): Liquid cooling penetration goes from 33% of new AI-DC racks (2025) → 50–70% (2030), and is physics-mandatory above 30kW/rack. The 800V architecture mandates 100% liquid cooling at 45°C inlets. ETN's Boyd Thermal acquisition (closed March 2026, $9.5B, $1.7B revenue at 80%+ DC mix) and Ecolab/CoolIT ($4.75B, March 2026) have reshaped this layer from "VRT incumbent" to three-player consolidation by 2027 (VRT / ETN-Boyd / Ecolab-CoolIT). Cooling/thermal is now treated as a load-bearing value-chain layer, not a sub-section of G2.

Where the deep-dive cohort sits:

• NVDA (L6/L7) — reference architecture the entire stack adapts to; "the rack is the product."
• TSM (L3/L5) — wafer + advanced-packaging chokepoint; CoWoS-L is the binding AI constraint.
• AVGO (L6/L7) — margin capture on every hyperscaler ASIC + Tomahawk scale-out.
• INTC (L3/L5/L6) — foundry pivot; binary on 14A.
• WOLF (L8a) — structural-transition cautionary tale; SiC substrate share 60%→34%.
• NVTS (L8b) — density bet on GaN; single-stage 800V-to-6V demos. Sits in a four-way race (Innoscience/NVTS/Infineon/TI) not a three-way race.
• TXN (L8b/L8c) — vertical-integration bet on GaN system BOM (not device share); ~5–7% discrete GaN share but the broadest analog stack per rack.
• ETN (G1/G2/G2T/G3) — grid-to-chip systems vendor post-Boyd Thermal; $700K–$2M per MW; $19.6B backlog.
• VRT (G1/G2/G2T/G3/G4) — incumbent UPS/PDU/cooling; $600K–$1.3M today → $1.2–2.8M Kyber era; $15B backlog / 2.9x book-to-bill.

Chokepoints the user emphasizes: TSMC CoWoS capacity, HBM (capacity + base-die TSMC logic consumption), ASML EUV, utility interconnect queues (3–7 years), box-builder lead times. C-COHERENCE adds two tier-2 chokepoints: GOES (grain-oriented electrical steel — Cleveland-Cliffs sole US producer, 128–144wk lead times, gates ETN backlog conversion — per Finding 7) and HFO refrigerants (Honeywell + Chemours >75% of R1234ze production — gates VRT cooling ramp — per Finding 13). These are structurally analogous to the foundry chokepoint at the silicon layer.

§ 043. Dominant Themes

3.1 The voltage stack is being redesigned at every layer simultaneously

The thread tying Notes 1, 2, and 3 together. HVDC at the grid. 800V DC at the building. 48V → 800V at the rack (OCP Mt. Diablo and NVIDIA Kyber paths competing through 2027). SiC/GaN replacing silicon in power-semi. BSPDN at the chip. "Power is no longer a supply problem. It has become a question of how to redesign the entire voltage stack from the power plant to the die" (per "The AI Power Crisis — Part 1"). Every layer of the stack gets a piece of this transition — chip vendors, box builders, equipment makers, connector vendors. This is the structural reason the cohort spans NVDA at one end and ETN/VRT at the other.

3.2 Chip-to-grid value-chain expansion: AI capex pass-through to power infrastructure

The user tracks this as a dollars-on-purchase-orders phenomenon, not a forecast. Vertiv Q4'25 organic orders +152% YoY; backlog $15.0B (+109% YoY); book-to-bill ~2.9x. Management reportedly stopped disclosing quarterly orders/backlog because the numbers had become "too extreme and too attention-grabbing" (per "The AI Power Crisis — Part 2"). Eaton Q4'25 datacenter orders ~3x YoY. Delta Electronics overtook Foxconn by market cap in January 2026. C-COHERENCE reinforces this with the $/MW asymmetry (Findings 8 + 11): ETN and VRT each capture 20–60x more dollar-volume per MW than the power-semi BOM layer. The load-bearing reason ETN/VRT sit in the deep-dive cohort is this dollar-volume reality, not just the narrative.

3.3 GaN/SiC competitive structure — REWRITTEN FOR C-COHERENCE

The prior "three-way GaN race" frame (Infineon scale / TI vertical / Navitas density) was incomplete. Per Finding 1 (C-NVTS-1 fan-out), the correct map is a four-way race with Innoscience at #1 (~30% share), NVTS #2 (~17%), then Infineon/TI/POWI/EPC at single digits by device share. Innoscience runs 8" GaN-on-Si IDM at scale, is on NVIDIA's 800VDC partner list, and is the cost-floor risk that was missing from the prior synthesis's competitive frame.

Per Finding 5 (C-TXN-1 fan-out), TI's bet is structurally different from the other three: TI's GaN device share is only ~5–7% globally. The vertical-integration thesis does not require TI to win discrete GaN device share. It requires TI to capture more system-BOM dollars by feeding internal GaN into the PMIC + isolated bus converter + multiphase buck stack that TI debuted at NVIDIA GTC March 2026 (97.6% efficiency, >2,000W/in³). TI is a system-BOM bet at L8b-L8c + L7 + L6 + L5, not a discrete socket capture at L8b/c alone. Per Finding 5 (refinement-log): "The GaN four-way race is by device share; TI's bet is at the system BOM, not the device socket."

The April 2 2026 ITC final determination in Infineon v. Innoscience (337-TA-1407) is the dated GaN-IP regime catalyst. Base case (~70% probability): Innoscience prevails (amplifies cost-floor risk for device-share competitors). A surprise Infineon win on ≥1 patent shifts the cohort GaN moat read materially positive.

On the SiC side: STMicro growth narrative complicated by auto softness; onsemi pivoting via Qorvo SiC JFET acquisition ($250M+ AI-DC revenue in 2025); Wolfspeed disintegrating from >60% substrate share to ~34% as Chinese competitors gain. "Structural transitions do not guarantee equal outcomes."

3.4 The supply chain — not the technology — chose 800V

The user's most distinctive analytical move. 800V was chosen not for physics but because Porsche, Hyundai, VW, Tesla, BYD, and the rest spent 5–7 years building 1200V SiC MOSFETs, 650V GaN FETs, HV connectors, laminated busbars, pyrofuses, and solid-state contactors at production scale for EVs. Hyperscalers step into that ecosystem with adaptation, not invention. As TI's Jeffrey Morroni is quoted: "the technology and semiconductor infrastructure that safely supports an 800V EV looks very similar to what an 800V rack infrastructure needs" (per "The AI Power Crisis — Part 2"). Automotive softness is a tailwind for power-semi vendors.

3.5 Cooling-transition pricing power — UPGRADED FOR C-COHERENCE

Liquid cooling penetration: 33% of new AI-DC racks (2025) → 50–70% (2030). Physics-mandatory above 30kW/rack. The 800V architecture mandates 100% liquid cooling at 45°C inlets. The Uptime Institute reports cooling systems accounted for 13% of datacenter failures in 2024 — the failure-consequence reality that drives incumbent pricing power.

Three-player consolidation (Finding 14 + Finding 6): Until March 2026, VRT held unchallenged CDU market leadership. Boyd Thermal-via-ETN ($9.5B, $1.7B revenue, 80%+ DC mix, closed March 2026) and Ecolab/CoolIT ($4.75B, March 2026) have created three well-capitalized competitors by 2027. VRT's cooling moat has compressed from wide to narrow. Quarterly bookings monitoring required to detect further erosion.

This theme has been upgraded from narrative thread to load-bearing structural theme on the basis of the quantified penetration curve and the M&A-driven competitive reset.

3.6 The rack is the new product

From per-GPU to per-rack: Blackwell GB200 NVL72 ships 72 GPUs, 36 Grace CPUs, integrated liquid cooling, $3M list. Rubin Kyber: 144 or 576 GPUs in one NVLink fabric. This matters because (a) Nvidia captures more BOM per deployment, (b) competitors must ship racks too, and (c) the bigger the scale-up domain the better MoE models perform. SuperMicro's DCBBS is highlighted as a positive. VRT's 70–120% per-MW content uplift in the Kyber era (per Finding 11) is the direct dollar expression of this theme at the box-builder layer.

3.7 The three bottlenecks: logic, memory, power

"Every news story about AI compute, every Nvidia earnings call, every export-control debate is ultimately about one of these three bottlenecks." Logic → TSMC. Memory → SK Hynix. Power → fragmented (utilities + box builders + gas turbine OEMs + nuclear + power semis). Bottlenecks are not independent: relieving one tightens the others.

3.8 Backlog conversion gating by tier-2 chokepoints — NEW THEME (C-COHERENCE)

Per Findings 7 + 13: Both ETN and VRT face binding tier-2 supply constraints that gate calendar conversion of orders to revenue — independent of demand. GOES (grain-oriented electrical steel) is ETN's analog of the foundry chokepoint: Cleveland-Cliffs is the sole US domestic producer, global lead times are 128–144 weeks (Q2 2025), and this is the binding constraint on ETN's $19.6B backlog conversion. HFO refrigerants (R1234ze) are VRT's: Honeywell + Chemours dominate global R1234ze production; EU F-Gas + US AIM Act force simultaneous cooling-industry transition; spot tightness in 2026–27 during VRT's max ramp is a production-limiting risk not visible in backlog math.

This mechanistically explains Open Question §2 / §15 from the prior synthesis: Schneider's "2028–2030 real market impact" framing is not simply a conservative corporate view — it reflects the physical reality that power-infra orders are real but conversion to revenue is gated by steel supply chains and refrigerant chemistry, not by demand. The calendar mismatch is real; the mechanisms are now named.

3.9 The unit cost of intelligence keeps falling, and that is bullish for compute demand

"Cost per token of AI output has fallen by orders of magnitude and continues to fall 2–4x per generation. Cheaper intelligence means more applications become economical" (per "The Semiconductor Industry: A Beginner's Companion"). Claude Code / Cursor / Devin are the first wave of applications whose unit economics already work at current token cost. Every layer of efficiency improvement (cheaper wafers, faster HBM, denser racks, MLA, MoE, FP4) compounds into more demand, not less.

3.10 The CUDA moat is changing shape, not breaking

CUDA + NVLink + TensorRT-LLM + Dynamo runs best on integrated Nvidia hardware. Triton + PyTorch 2.0 narrowed the floor; AMD ROCm "solved" the 80% case in 2024; OpenAI's MI450X commitment is the live test of whether AMD can close the last 10–20%. User's working answer: "tentatively yes" — alternatives constrain Nvidia's pricing power on hyperscaler workloads but cannot displace it on integrated cluster-class problems.

3.11 Custom silicon is the hyperscaler counter-leverage

TPUv7, Trainium3 + Project Rainier, Maia 2, OpenAI's Broadcom-partnered chip in 2027 — every hyperscaler has captive silicon, almost all designed with Broadcom. The user reads this as: Nvidia still wins, but pricing power on high-end hyperscaler buys is capped. "Broadcom is structurally the best ASIC bet — captures margin on every TPU, every MTIA, every OpenAI chip, without bearing the product risk of any one of them."

3.12 The embedded-analog cycle: destocking → restock (TXN-specific)

TXN's distinctive frame is not "embedded analog destock" but "an analog/embedded-power vendor that already paid for the GaN capacity AI is about to need." Q1'26 industrial +30%, data center +90% YoY, distributor inventory at multi-year lows, book-to-bill above 1.0 — the restock is in the prints. The destock-to-restock cycle is a downstream PM question; the cohort frame puts TXN on the supply-meets-demand-curve-crossover thesis.

3.13 Advanced packaging is the new process

Classical transistor shrinking has slowed; cost per transistor flat since N7 and rising at N2/A16. Density comes from CoWoS, SoIC, EMIB, Foveros, hybrid bonding. "TSMC's 'process lead' is now significantly an 'advanced packaging lead.'" Hybrid bonding tools (BESI, AMAT, Shibaura) are themselves a chokepoint.

3.14 The China parallel stack: lagging but self-sufficient

SMIC + CXMT + YMTC + Huawei Ascend + Biren + Moore Threads form a coherent parallel stack, lagging 2–3 years on logic, 3–4 years on HBM. Sufficient for domestic demand. Contrarian point echoing SemiAnalysis: binding constraints for China are HBM + DUV immersion + KLA inspection, not leading-edge logic per se. CloudMatrix 384 demonstrates "architecture innovation can partially substitute for process-node lag."

3.15 Power is the ultimate binding constraint

US electricity demand was flat for 15 years; now growing 3–5% per year. Transmission 7–15 years, generation 3–6, interconnect queues 3–7. "Each GW of AI datacenter represents ~$10–12 billion in annual revenue potential. Every 6-month delay in energizing a build costs billions in forgone compute sales." Operators willing to bypass the grid (xAI Colossus, Stargate Texas 2.3 GW gas) move fastest. Box-builder backlog is a leading indicator of where the binding constraint has moved: from "can we get the chip" to "can we power the chip."

§ 054. Catalysts & Inflection Points

Near-term (0–6 months)

• April 2, 2026 — ITC FD, Infineon v. Innoscience (337-TA-1407). The single most important GaN-IP regime event in 2026. Base case: Innoscience prevails (~70% probability). A surprise Infineon win shifts cohort GaN moat read materially. Affects NVTS conviction directly; also TXN and Infineon.
• Mt. Diablo / Diablo 400 deployment — 800V path preserving AC backbone. Microsoft/Meta/Google sponsorship.
• Vertiv / Eaton Q1–Q2 2026 order books — each print calibrates the backlog-to-revenue conversion thesis.
• VRT EMEA Q2 2026 print — follow-on read on Q1 2026 -20% YoY. Two more negative quarters would confirm structural Schneider share loss in home market.
• HBM4 ramp into Rubin / MI450 / TPUv7 — bus doubles to 2048 bits; SK Hynix continues to lead.

Medium (6–24 months)

• September 13, 2026 — MOFCOM antidumping FD on TXN. Bernstein sizes ~11.4% of revenue exposed; 3–6% at meaningful adverse-outcome risk. Largest near-term asymmetric downside in TXN thesis. Catalyst-aware sizing: TXN is a Q1–Q3 2026 long defended through Q4 binary.
• TSMC A16 H2 2026 — first TSMC node with backside power.
• Intel 18A external customer ramp — Microsoft and DoD signed; volume small but the only live 14A-precursor test.
• Rubin / R100 launch (2026) — N3P, HBM4, NVLink 6, Kyber rack platform.
• AMD MI450X with HBM4 and UALink — OpenAI anchor; live competitive test.
• NVIDIA 800V DC architecture (Kyber, 2027) — beginning of 1 MW racks; the revenue inflection for VRT/ETN content per MW.
• Mobility Segment spin-off (ETN, Q1 2027) — the single most important structural re-rating catalyst for ETN; strips ~$3B low-margin Vehicle/eMobility drag.
• Boyd Thermal integration milestones (ETN, 2026–27) — Q2/Q3 2026 cooling-revenue run-rate vs $1.7B target is the integration-execution test.
• VRT South Carolina 7x capacity ramp — binding backlog-conversion constraint through mid-2027; 35–50% probability of 6-month slip.
• Ironton Ohio (VRT thermal, +45%, Q2 2027 operational) + Mexicali (VRT power, +45%).
• FERC Order 1920 RTO/ISO compliance filings Q2–Q3 2026 — crystallizes $4.8B+ PJM transmission upgrade pipeline addressable by ETN.
• TI 300mm GaN production transition — pilot complete; volume is the inflection calibrating vertical integration vs Infineon scale.
• CPO ramp: Quantum-X / Spectrum-X Photonics shipping 2026.
• High-NA EUV adoption at TSMC and Samsung — if TSMC commits, ASML revenue cycle accelerates.

Structural (>2 years)

• Vera Rubin Ultra (2027) + co-packaged optics generalization at the GPU package.
• Schneider's "real market impact of 800V DC, 2028–2030." Single most important cohort timing check; now mechanistically explained by GOES + HFO refrigerant + OEM capacity ramp constraints (Finding 7 + 13).
• Intel 14A with DSA (2027 target) — "if it works, Intel is back. If it doesn't, permanently sidelined."
• TSMC A14/A10 with High-NA EUV.
• First commercial US SMR (2029+) — user is skeptical of any earlier date.
• Three-player liquid cooling market share resolution (2027–2028) — VRT incumbent vs ETN/Boyd vs Ecolab/CoolIT.
• 300mm GaN volume at Infineon, TI — wafer economics step-change.
• Solid-state transformer commercial deployment — $115M market (2025), $375M projected by 2033 at 16% CAGR.

§ 065. Tailwinds & Headwinds

§ 076. Contested Claims & Open Questions

Resolved / Updated by C-COHERENCE Pass

Open Question §1 (Taiwan-tail unhedged) — MATERIALLY CLOSED. TXN has ~10–15% Taiwan exposure vs 60–90% for NVDA/AVGO/TSM/NVTS. ETN has minimal Taiwan exposure. VRT has zero Taiwan production exposure. Three of the four expansion names hedge Taiwan-tail. The cohort's residual Taiwan exposure is now concentrated in NVDA/AVGO/TSM/NVTS. The prior Open Question "the cohort is not hedging Taiwan-tail at all" is materially closed by this expansion. (Per Finding 4, refinement-log C-TXN-1.)

Open Question §2 / §15 (Schneider 2028-2030 calendar mismatch) — MECHANISTICALLY EXPLAINED. The mismatch is real; the mechanisms are now named: GOES (128–144wk lead times, Cleveland-Cliffs sole US producer) gates ETN; HFO refrigerants (Honeywell/Chemours R1234ze concentration) gates VRT. Calendar mismatch on backlog conversion is the cohort's most important "we're early" trap, and it is now structurally understood rather than merely flagged. (Per Findings 7 + 13, refinement-log.)

§16 (ETN corpus thinness) — RESOLVED. Analysts went beyond corpus. Boyd Thermal acquisition (closed March 2026, $9.5B, $1.7B revenue at 80%+ DC mix) was the single most consequential ETN structural development not in the vault. ETN deep-dive is substantively complete. The corpus thinness flag is retired; the ETN thesis is now grounded in primary research, filings, OCP materials, and earnings transcripts.

Theme §3 (GaN three-way race) — CORRECTED. The "Infineon scale / TI vertical / Navitas density" three-way frame was incomplete. Innoscience is #1 at ~30% share. The four-way frame is the truth. See Section 3.3 above.

Active Open Questions

1. Wolfspeed structural-transition cautionary tale. The user's only explicit -2 sentiment. Who else in the corpus is riding the right wave but losing share? ST is flagged as adjacent.
2. Single-stage 800V-to-low-voltage architecture (Navitas). Demos exist; mainstream adoption is "too early to say." The contested question is whether density beats scale (Infineon) or vertical integration (TI) over 2027–2030. Central question for NVTS deep-dive. No major box-builder has a publicly named Navitas-anchored 800VDC reference design as of May 2026 (Finding 3).
3. The GaN four-way race timing. Innoscience is IDM at scale with NVIDIA 800VDC partner status. Infineon shipped 300mm samples late 2025. TI completed 300mm pilot. Navitas has no comparable 300mm anchor. Does the 300mm cost curve dominate before density advantage matters? Does Innoscience move up from discrete to GaN-IC products (the NVTS kill scenario)?
4. AI-capex single-factor concentration — NOW THE COHORT'S LARGEST RESIDUAL RISK. ETN (16–19% AI-DC mix, growing to 22–26% post-Mobility spin) and VRT (65–80% AI-DC mix) are both AI-capex amplifiers. TXN's diversified base partially offsets. Combined ETN+VRT must be capped at ≤1.5–2.0x TXN NAV (portfolio-construction constraint from Finding 16). The upcoming D1 portfolio summary must enforce this.
5. Three-player cooling consolidation 2027. VRT's incumbent CDU lead is being contested by Boyd-via-ETN and CoolIT-via-Ecolab. Quarterly bookings monitoring required to detect VRT share erosion.
6. VRT EMEA -20% YoY Q1 2026 — first geographic crack. May be specification-share loss to Schneider in home market. Watch Q2 2026 print. Two more negative quarters = structural loss; one quarter = timing.
7. Mexico manufacturing tariff as cohort-specific risk not in the original Taiwan/China framing. 25% Section 232 scenario adds $150–250M annual COGS to ETN with only partial pass-through. VRT's Mexicali facility also exposed. A Mexico row must be added to the cohort's geographic risk matrix.
8. GPU useful life. The Michael Burry / CoreWeave debate. User has deployed Aravolta telemetry on their own cluster to answer it. Live.
9. Whether Intel 14A's DSA "magic bullet" works. Binary. "If it works, Intel is back. If it doesn't, permanently sidelined."
10. Whether Rapidus succeeds where prior Japanese 2nm efforts failed. User openly skeptical.
11. Whether SMR claims for 2027–2028 deployment are ever real. User: "aspirational, not realistic."
12. NVIDIA Kyber design-win for NVTS — ecosystem partner or primary GaN-IC supplier? As of May 2026: ecosystem partner (14-vendor list); Infineon is "lead partner." A GTC 2026 re-designation to primary supplier is the highest-asymmetry near-term catalyst.
13. Whether DeepSeek-style efficiency gains compress total compute demand or expand it. User's view: expand. The foundational denominator assumption for the entire sector long thesis.
14. Whether the OCP Mt. Diablo path or NVIDIA's full-facility 800 VDC Kyber path wins. Both converge on 800V; timing question. User: "most realistic before 2027 is probably hybrid."
15. Whether Samsung Foundry can win confidence back. Yield problems since SF3; pursuing Tesla / Qualcomm externally.

§ 087. The Company Universe

166 companies in the ledger. The 9-name deep-dive cohort is flagged in companies.json via deepDiveCohort: true, cohortTier, convictionTier, and cohortArchitectureRole (added in version 3). Sorted by absolute sentiment descending.

Cohort architecture sub-section: Chip-layer names (NVTS/TXN at L8b/L8c) and grid/system-layer names (ETN/VRT at G1-G4) are held as independent positions, not as a chain. Box-builders are vendor-agnostic on power-semi supplier by commercial design. ETN+VRT combined exposure capped at ≤1.5–2.0x TXN NAV.

*Innoscience and Ecolab/CoolIT added to ledger by C-COHERENCE pass based on findings surfaced by analysts.

Sentiment buckets (168 total, +2 new names added in C-COHERENCE — Innoscience and Ecolab/CoolIT):

• Strong long (+2): 18 names
• Lean long (+1): 61 names (added Innoscience at +1, Ecolab/CoolIT at +1)
• Neutral / mixed / open (0): 81 names
• Lean short (-1): 7 names
• Strong short (-2): 1 name (Wolfspeed)

Deep-dive cohort (9 names total — unchanged):

• High conviction (core): NVDA, TSM, AVGO, TXN
• Medium conviction (completion): ETN (buy on weakness), VRT (probe — valuation)
• Low conviction (probe): NVTS
• Short high conviction: WOLF
• Short medium conviction: INTC

Net long-tilt: 7 longs vs 2 shorts. Taiwan-tail materially closed by TXN/ETN/VRT hedge; residual concentration in AI-capex single-factor (ETN+VRT combined cap is the portfolio discipline rule).

Themes identified: 15 dominant themes (added Theme 3.8 "Backlog conversion gating by tier-2 chokepoints"; upgraded Theme 3.5 cooling-transition to load-bearing; corrected Theme 3.3 GaN competitive structure to four-way race).

Off-topic / mis-tagged notes: None. The EV makers and the Boston Computer Exchange sidebar remain appropriate given the explicit "supply chain chose 800V" thesis. All 4 notes contribute load-bearing content.

C-COHERENCE changes summary: Two material defects corrected (GaN three-way race frame; missing $/MW asymmetry statement at G1-G4). One new load-bearing layer added (G2T cooling/thermal). One new load-bearing theme added (backlog conversion gating by tier-2 chokepoints). Three open questions resolved (Taiwan-tail, Schneider calendar mismatch mechanistically explained, ETN corpus thinness retired). Seven new open questions added. Two new companies added to ledger (Innoscience, Ecolab/CoolIT). Conviction tiers and cohort architecture roles finalized across all 9 deep-dive names. companies.json bumped to version 3.