§ ticker  ·  AVGO  ·  long · conv. 4/5 · medium · CORE
PM thesis · AVGO · Broadcom Inc. · 2026-05-03 · cohort architecture role: CORE

AVGO

Broadcom Inc.

Long
Conviction
  4 / 5
Sizing
Medium · overruled from 5
Horizon
12–24 months
Entry
30% reserved

The cleanest "arms-merchant to the hyperscaler ASIC counter-leverage" name in the cohort: ~70% share of top-tier custom XPU programs after Marvell's Trainium 3/4 stumble, a one-generation Ethernet switch lead with Tomahawk 6, and a $73B AI backlog with cost-plus-flavored design-services contracts. The thesis works because every credible hyperscaler counter-Nvidia move flows through Broadcom IP. What breaks it is not competition — it is valuation × duration. At ~31× forward P/E and ~1.0% "real" FCF yield post-SBC, the equity is the highest-duration name in the cohort.

§ 01

Asymmetry · ~1.3–1.5 : 1.

tightest in cohort · medium not large
−40% −25% today +30% +45% −25 to −35% if wrong +30 to +45% if right RATIO 1.3 : 1
Tightest in the cohort. Below the >2:1 we want for a high-conviction add. The second mathematical reason for sizing medium not large — the asymmetry is positive but a long carried because the underlying business is durable, not because the entry is asymmetric.

Better than NVDA at current levels (NVDA closer to symmetric on raw upside/downside framing), worse than TSM (TSM is the cleanest 2:1 because the bottleneck math is unambiguous and the multiple has not stretched as far). The "moat moved" tension on AVGO catches both sides — the share-shift mechanism cuts ASIC partner share and loops back to NVIDIA bundle attach.

§ 02

Competitive position · the Marvell stumble cemented it.

5-axis · monopoly restored
COST · 4 SWITCH · 5 NET · 3 INTANG · 5 SCALE · 4
5-axis moat scoring · AVGO · per competitor.md Phase 3

Switching costs are 5 — physical, not contractual.

Each XPU program is a 3–5 year multi-generation engagement once started. Google TPU lineage with Broadcom now spans a decade; Meta MTIA is locked through multi-gigawatt deployment commitments. Architectural choices compound across generations and would cost $hundreds-of-millions and 18+ months to switch.

Intangibles are 5 — generational IP moat.

The 224G SerDes IP is roughly 12–18 months ahead of merchant alternatives. ASIC physical design, RDL interposer routing, signal integrity expertise codified in tens of thousands of person-years. The Marvell-Trainium 2 stumble (RDL interposer execution failure) is a live demonstration that this IP is not commoditized.

Network effects are 3 — indirect, not classic.

SerDes IP / Ethernet ecosystem pull, UALink consortium leadership. Tomahawk's 224G SerDes interoperability with NIC vendors, optics, and customers' in-house silicon. Not a two-sided-market network effect.

Verdict Wide · strengthening. Pass-through pricing power converts supply chain risk into customer risk. AVGO has structural pricing power on design-services and IP-licensing layers (high margin, extreme switching costs), pass-through economics on the silicon layer (TSMC and Hynix capture upside). A healthy split.
§ 03

Supply chain · pass-through pricing power.

cost-plus design services · physical lock-in

Five of six supply-chain risk vectors score 4–5 — but pass-through scores 1. That single feature recasts the whole picture. AVGO bears shipment risk (CoWoS allocation), not pricing risk. AI chip GM held ~65% in FY25 with massive HBM4/CoWoS-L cost inflation flowing through.

Diagram · supplier flow · risk-codedconcentrated single-source · pass-through to customer
flowchart LR
  classDef sev fill:oklch(32% 0.10 28),stroke:oklch(60% 0.14 28),color:oklch(95% 0.05 28),font-family:'Geist Mono',font-size:11px
  classDef elev fill:oklch(35% 0.10 95),stroke:oklch(72% 0.13 95),color:oklch(95% 0.04 95),font-family:'Geist Mono',font-size:11px
  classDef ok fill:oklch(28% 0.06 230),stroke:oklch(58% 0.08 230),color:oklch(94% 0.04 230),font-family:'Geist Mono',font-size:11px
  classDef anchor fill:oklch(40% 0.13 95),stroke:oklch(80% 0.13 95),color:oklch(98% 0.05 95),font-family:'Geist Mono',font-weight:600,font-size:13px

  ASML[ASML EUV
sole-source]:::sev BESI[BESI / Shibaura
HBM4 hybrid bonding]:::sev TSMC[TSMC N3 / N2
~150K wafers · ~15% CoWoS]:::sev COWOS[TSMC CoWoS-L
~150K booking 2026]:::sev HYNIX[SK Hynix HBM4
primary]:::elev SAMM[Samsung HBM3E
>60% Google TPU]:::elev COH[Coherent / Lumentum
EML lasers]:::elev AVGO{{Broadcom
224G SerDes IP
cost-plus design services}}:::anchor GOOG[Google TPU
~10–12% rev]:::ok META[Meta MTIA]:::ok BYTE[ByteDance ASIC]:::ok OAI[OpenAI 2027 chip]:::ok MSFT[Microsoft Maia 2]:::ok APPL[Apple AFM
under contract]:::ok AAPL_RF[Apple Wireless RF
~20% rev]:::ok ASML --> TSMC BESI --> COWOS TSMC --> AVGO COWOS --> AVGO HYNIX --> AVGO SAMM --> AVGO COH --> AVGO AVGO --> GOOG AVGO --> META AVGO --> BYTE AVGO --> OAI AVGO --> MSFT AVGO --> APPL AVGO --> AAPL_RF
Taiwan tail · TSMC sole-source for both leading-edge wafers AND CoWoS-L · two stacked single points of failure

Stress scenarios

Scenario · CoWoS-L allocation squeeze
base

The live case 2026–27. TSMC prioritizes NVIDIA (~60%); AVGO's allocation bounded by what NVIDIA does not take. ~$25–35B of AI silicon at current ASPs vs the $100B 2027 target.

Pass-through pricing
1 / 5

1 = strongest. Q1 FY26 blended GM 77% with AI revenue +106% YoY. Massive cost inflation flowing through to customers. The single most underappreciated structural feature.

Customer set growth
3 → 5 → 6

Named hyperscaler ASIC customers in 18 months. Apple AFM and OpenAI 2027 chip "next two." Concentration is increasing — but on materially better terms.

§ 04

Customer & end-market.

AI ASIC compounding · VMware ballast
FY25 end-market AI · Networking ASIC · 33% VMware · 26% Wireless · 18% Server storage · 8% Broadband · 7% Industrial · 8%
FY25 mix · multi-cycle business · VMware mutes single-end-market volatility
CUSTOMER CONCENTRATION · per 10-K + cohort context
Apple (Wireless)
~20%
Google (TPU)
~10–12%
Top 3
~35–40%
Top 5
~50%+

Key trend: identity of the top concentration is rotating from Wireless/Apple (mature, declining as % of mix) to Semiconductor Solutions/AI ASIC (Google + Meta + emerging OpenAI). Total concentration increasing but on materially stickier multi-year ASIC roadmap dependency.

$73B AI backlog — anchor for near-term steepness, not channel fill.

§ 05

Catalyst calendar.

Q4 FY26 print is the dominant binary
Q2 26 Q3 26 Q4 26 Q1 27 Q2 27 2028+ H2 2026 · convergence ↑ bull TSMC A16 backside power OpenAI Broadcom chip ramp Anthropic 400K TPU VMware SAMR sunset ⇄ binary Q2 FY26 print Spectrum-X1600 vs Tomahawk 6 Q4 FY26 — $40B AI cadence ↓ bear EC VMware compliance Section 232 decision CMA Section 18 NVLink Fusion ramp Hock Tan succession risk
The Q4 FY26 print (Dec 2026) is the highest-information catalyst — confirms or surfaces the gap to the $100B 2027 target.
§ 06

Kill criteria.

7 · observable · time-bounded
  1. A named hyperscaler explicitly cancels or deprioritizes a multi-year ASIC program with Broadcom in any of the next 4 quarters. Google announces TPU v(N+1) with non-Broadcom physical-design partner, Meta moves MTIA v3+ in-house, or ByteDance pulls allocation.
  2. AI semiconductor gross margin compresses by >500 bps in any single quarter without clearly disclosed mix-shift. Hard floor of 60% AI chip GM through FY26.
  3. AI revenue cadence comes in below $36B for FY26 (implied run-rate is ~$40B+ from Q1's $8.4B). A miss of >10% breaks reverse-DCF math.
  4. SBC drifts above 13% of revenue or buyback pace falls below dilution pace for two consecutive quarters. Means structural SBC re-rating widening rather than stabilizing.
  5. EC initiates formal Article 8(5) modification proceedings on VMware behavioral commitments. Flips from "bounded behavioral remedy" to "structural pricing constraint."
  6. Section 232 outcome includes Taiwan-origin tariff >15% with no CHIPS-Arizona carve-out. Below 15% or with carve-outs is digestible; above is 300–600 bps GM compression.
  7. Hock Tan signals retirement / transition before announced succession plan with capital allocation continuity. The entire VMware-style playbook is one CEO.
"Captures margin on every TPU, every MTIA, every OpenAI chip, without bearing the product risk of any one of them."— SemiAnalysis · cited by user · the framing the cohort is built around