NVTS

Navitas Semiconductor

The highest-asymmetry public expression of the "single-stage 800V-to-6V GaN-IC architecture wins the 2027 Kyber rack socket" bet, riding on a confirmed-but-non-exclusive NVIDIA 800V partnership and a genuinely first-mover integrated-IC patent estate. The trade only works if NVTS converts the $2.4B lifetime design-in pipeline into a named >10% AI-DC customer — none disclosed today — through the simultaneous TSMC-exit / PSMC-ramp / GF-Burlington-qualification triple foundry transition completing by July 2027. At 82.7× EV/Sales on revenue down 45% YoY with no LTAs and zero CHIPS direct grants, this is a venture-sized option premium printed on a public ticker.

This section decides the probe sizing, and the math is honestly tight. The asymmetry does NOT clear the 2:1 bar I'd want for a real position. Probe sizing acknowledges the modal outcome is closer to break-even than to bull-case 2×. The path-dependency — capex-light · 7-year runway · single well-timed Kyber design-in announcement re-rates 30%+ in a news cycle — justifies probe sizing over outright pass.

The cohort frame's "three-way GaN race" was incomplete. Per Finding 1: Innoscience took ~30% global GaN share to NVTS's ~17% on the back of 8" GaN-on-Si IDM scale, and is the sole Chinese partner on NVIDIA's 800VDC list. The cohort thesis must survive Innoscience taking the discrete tier (commodity 100V/650V) while NVTS holds the IC tier (integrated 800V→6V single-stage).

The April 2 2026 ITC FD in Infineon v. Innoscience (337-TA-1407) is the single most important regulatory event on the NVTS calendar in 2026. ALJ initial determination already favored Innoscience on two patents; Commission affirms expected ~70%. Base case: Innoscience prevails (bear-confirming for NVTS). A surprise patent-holds outcome would benefit Infineon more than NVTS but would not invalidate the NVTS thesis.

NVTS production is currently ~85–90% Taiwan (TSMC GaN through July 2027, PSMC ramping in Zhunan, Amkor packaging in Asia). The GF Burlington leg is the only US-domestic escape valve and it's small and late. NVTS adds Taiwan-tail beta through July 2027, then partially diversifies.

flowchart LR
  classDef sev fill:#3a1a18,stroke:#b85a3c,color:#fde0d8,font-family:'Geist Mono',font-size:11px
  classDef elev fill:#3a2e1a,stroke:#c8a04a,color:#fef3d6,font-family:'Geist Mono',font-size:11px
  classDef ok fill:#1c1f28,stroke:#5a6878,color:#cdd2da,font-family:'Geist Mono',font-size:11px
  classDef anchor fill:#5a4218,stroke:#e8c46a,color:#fff5d8,font-family:'Geist Mono',font-weight:600,font-size:13px

  GAL["Gallium
China dominant
export-control retaliation tail"]:::sev
  TSMC["TSMC GaN
exits end-July 2027
cliff"]:::sev
  PSMC["PSMC 100V
HVM 1H 2026
650V ramp 12–24mo"]:::elev
  GFB["GF Burlington
tape-out late 2026"]:::elev
  AMK["Amkor Asia
OSAT"]:::ok

  NVTS{{NVTS}}:::anchor

  NV["NVIDIA Kyber
14-vendor ecosystem list"]:::elev
  VRT["Vertiv · ETN · Schneider · Delta
no named NVTS reference design"]:::elev
  CN["China mobile legacy
~50% of revenue"]:::sev

  GAL --> TSMC
  GAL --> PSMC
  TSMC --> NVTS
  PSMC --> NVTS
  GFB --> NVTS
  AMK --> NVTS
  NVTS --> NV
  NVTS --> VRT
  NVTS --> CN
    

The triple foundry transition is the single biggest execution risk. TSMC GaN exits end-July 2027 (cliff). PSMC 100V production starts H1 2026; PSMC 650V transitions over 12–24 months; GF Burlington production "later 2026." All must qualify into Rubin Ultra design-in windows. Falsifiable by: any quarterly print between Q1'26 and Q2'27 disclosing PSMC qualification slip OR GF Burlington tape-out delay.

1. Innoscience cracks the AI-DC reference design tier. Mechanism: Innoscience moves up the value curve from discrete commodity GaN into integrated GaN-IC products at 8" wafer economics. NVTS's "density beats scale" thesis loses both axes simultaneously. Watch: Innoscience product roadmap announcements at IEDM December 2026 / APEC 2026 disclosing GaN-IC half-bridge or driver-integrated 100V/650V parts. Action: exit; consider reversing to short on conviction 3.
2. TSMC-to-PSMC/GF process portability fails for the GaNSafe IC family. Mechanism: integrated-IC products may not port cleanly to PSMC's 180nm CMOS or GF Burlington's licensed-from-TSMC process. Watch: any quarterly call commentary disclosing "GaNSafe IC requalification" or "process portability investment." Action: any disclosed slip in PSMC 650V engineering-sample qualification beyond Q4 2026 forces immediate exit.
3. Equity raise into a depressed price. Mechanism: management raises ATM into weakness rather than pausing for design-win catalysts → signals capital-structure desperation, lacking confidence in near-term catalysts, recursive dilution. Watch: ATM utilization disclosure in Q1/Q2 FY26 10-Qs. Action: any ATM/S-3 raise above $50M into a price below $12 forces exit.