§ cohort  ·  Themes  ·  15 themes · 3 status tiers
Filed 2026-05-04  ·  from synthesis §3 (15 themes · v3 ordering)

Fifteen themes, three positions.

Mapped on conviction strength × cohort centrality. Voltage stack at #1; chip-to-grid expansion at #2; GaN four-way race (corrected) at #3; backlog conversion gating as the new load-bearing theme. The pure-semi themes (CUDA moat, custom silicon) survive but are explicitly downgraded to mid-list.

§ 01

The themes, plotted.

conviction × centrality · 15 themes

Vertical axis = conviction strength (how confident the cohort is in this theme). Horizontal axis = cohort centrality (how many cohort positions depend on it). The four highest-stake themes cluster top-right; the structural-cautionary themes (cost-flat, single-stage uncertainty) sit lower-conviction.

1 name 2–3 names 4–5 names 6–7 names all 9 names load-bearing structural contested CONVICTION COHORT CENTRALITY → Specialty · single-name Load-bearing · cohort-wide Open question Cyclical · widely felt #1 Voltage stack redesigned at every layer simultaneously #2 Chip-to-grid expansion VRT $15B · ETN 3× orders #3 GaN four-way race CORRECTED · Innoscience #1 #4 Supply chose 800V EV → AI infra crossover #5 Cooling-transition pricing UPGRADED · load-bearing #6 Rack-as-product #7 Three bottlenecks #8 Backlog gating NEW · GOES + HFO #9 Unit cost ↓ #10 CUDA moat shape DOWNGRADED #11 Custom silicon #12 Embedded-analog TXN-specific #13 Advanced packaging #14 China parallel stack #15 Power binding AI-capex concentration LARGEST RESIDUAL RISK 15 dominant themes · plotted on conviction × cohort centrality v3 ordering · synthesis §3 cohort-supportive downgraded / mixed structural risk disk size = cohort consensus weight
Source · synthesis.md §3 (15 themes ordered by load-bearing weight). Three structural themes corrected/added in C-COHERENCE: #3 GaN four-way race (Innoscience #1), #5 cooling-transition upgraded to load-bearing (post-M&A), #8 backlog conversion gating added as new theme.
§ 02

The 15 themes, with positions.

v3 ordering · most cohort-load-bearing first
#ThemeCohort positionsStatus
1 The voltage stack is being redesigned at every layer simultaneously. HVDC at the grid · 800V DC at the building · 48V→800V at the rack · GaN/SiC replacing silicon · BSPDN at the die. Per "AI Power Crisis Part 1": "Power is no longer a supply problem. It has become a question of how to redesign the entire voltage stack from the power plant to the die." TXN · NVTS · ETN · VRT · WOLF · TSM Load-bearing
2 Chip-to-grid value-chain expansion · AI-capex passthrough. VRT Q4'25 organic orders +152% YoY · backlog $15B at 2.9× B2B. ETN Q4'25 DC orders ~3× YoY. Delta overtook Foxconn by mkt cap January 2026. $/MW asymmetry: G1–G4 captures 20–60× more dollar-volume than L8b/L8c per MW. VRT · ETN Load-bearing
3 GaN/SiC competitive structure · four-way race (corrected). Innoscience #1 ~30% · NVTS ~17% · POWI ~17% · EPC ~12–15% · IFX ~10% · TXN ~5–7%. Per Finding 5: TI's bet is at the system BOM, not the device socket. Prior synthesis's three-way frame was incomplete. NVTS · TXN Corrected
4 The supply chain — not the technology — chose 800V. EV industry built a mature 1200V SiC / 650V GaN / HV connector ecosystem over 5–7 years. AI infrastructure inherits it. Per TI's Jeffrey Morroni: "the technology and semiconductor infrastructure that safely supports an 800V EV looks very similar to what an 800V rack infrastructure needs." TXN · NVTS · IFX · ON Load-bearing
5 Cooling-transition pricing power · upgraded. Liquid cooling penetration 33% (2025) → 50–70% (2030). 800V mandates 100% liquid cooling. Three-player consolidation (VRT / ETN-Boyd / Ecolab-CoolIT) by 2027. The Uptime Institute reports cooling = 13% of DC failures in 2024. VRT · ETN Upgraded
6 The rack is the new product. NVL72: 72 GPUs, 36 Grace, integrated liquid cooling, $3M list. Rubin Kyber: 144 or 576 GPUs in one NVLink fabric. VRT 70–120% per-MW content uplift in Kyber era is the dollar expression at the box-builder layer. NVDA · VRT Load-bearing
7 Three bottlenecks · logic, memory, power. Logic → TSMC. Memory → SK Hynix. Power → fragmented (utilities + box builders + gas turbine OEMs + nuclear + power semis). Bottlenecks compound: relieving one tightens the others. TSM · VRT · ETN Load-bearing
8 Backlog conversion gating by tier-2 chokepoints · NEW. GOES (Cleveland-Cliffs sole US, 128–144wk lead times) gates ETN. HFO refrigerants (Honeywell + Chemours >75% R1234ze) gates VRT. Schneider's 2028–2030 framing is the physical reality of order-to-revenue conversion, not a demand-side hedge. ETN · VRT NEW · structural
9 Unit cost of intelligence keeps falling · 2–4× per generation. Cheaper intelligence pulls in more applications. Claude Code · Cursor · Devin are first wave. Every layer of efficiency (cheaper wafers · faster HBM · denser racks · MLA · MoE · FP4) compounds into more demand, not less. NVDA · TSM · AVGO Foundational
10 CUDA moat is changing shape, not breaking · downgraded. CUDA + NVLink + TensorRT-LLM + Dynamo runs best on integrated NVIDIA hardware. ROCm "solved" 80% case in 2024; OpenAI MI450X is the live test of the last 10–20%. Working answer: "tentatively yes" — alternatives constrain pricing power on hyperscaler workloads but cannot displace on integrated cluster-class problems. NVDA Downgraded
11 Custom silicon is hyperscaler counter-leverage. TPUv7 · Trainium3 + Project Rainier · Maia 2 · OpenAI's Broadcom-partnered chip in 2027 — almost all designed with Broadcom. NVIDIA still wins, but pricing power on high-end hyperscaler buys is capped. AVGO · NVDA Live tension
12 Embedded-analog cycle · destocking → restock · TXN-specific. Q1'26 industrial +30%, data center +90% YoY, distributor inventory at multi-year lows, book-to-bill above 1.0. Restock is in the prints. The destock-to-restock cycle is downstream PM question; the cohort frame puts TXN on the supply-meets-demand crossover thesis. TXN Single-name
13 Advanced packaging is the new process. Cost per transistor flat since N7 and rising at N2/A16. Density comes from CoWoS · SoIC · EMIB · Foveros · hybrid bonding. Hybrid bonding tools (BESI · AMAT · Shibaura) are themselves a chokepoint. "TSMC's 'process lead' is now significantly an 'advanced packaging lead.'" TSM · INTC Structural
14 The China parallel stack · lagging but self-sufficient. SMIC + CXMT + YMTC + Huawei Ascend + Biren form a coherent parallel stack, lagging 2–3 years on logic, 3–4 years on HBM. Binding constraints: HBM + DUV immersion + KLA inspection, not leading-edge logic per se. CloudMatrix 384 demonstrates "architecture innovation can partially substitute for process-node lag." TSM · INTC Contested
15 Power is the ultimate binding constraint. US electricity demand was flat for 15 years; now growing 3–5% per year. Transmission 7–15 years; generation 3–6; interconnect queues 3–7. Each GW of AI-DC = ~$10–12B annual revenue potential. Operators bypassing the grid (xAI Colossus, Stargate Texas 2.3GW gas) move fastest. ETN · VRT Macro
§ 03

What changed in v3.

3 resolved · 7 new · 1 corrected
Resolved 3

Taiwan-tail unhedged · Schneider 2028–2030 mismatch · ETN corpus thinness — all materially closed by C-COHERENCE pass.

Corrected 1

GaN three-way race → four-way race. Innoscience #1 at ~30% share was the silent omission. Cohort thesis must inherit this correction.

New open 7

AI-capex single-factor (largest residual) · cooling 3-player consolidation · VRT EMEA crack · Mexico tariff · Innoscience GaN-IC move-up · TSMC GaN exit / NVTS triple foundry transition · MOFCOM TXN binary.

Upgraded 2

Cooling-transition pricing power → load-bearing (Theme #5). Backlog conversion gating → new load-bearing theme (#8). G2T promoted to its own value-chain layer.

Theme-anchored ticker pages

Cohort views

Source memos