A continuous voltage system, plotted.

From the substation to the transistor — 16 layers, 9 cohort names, and a 20–60× asymmetry in dollar-volume between the electrical layers and the silicon they feed.

Every MW of AI-DC capacity built captures value at every layer of the stack. The dollars compound at the electrical layer because the equipment is heavier, the field service is harder, and the certification cycles are longer. The silicon layer captures the margin per dollar; the electrical layer captures the dollars. This single asymmetry is the load-bearing argument for ETN and VRT inside a "semiconductor" cohort.

Read this once. The G1–G4 layers capture $700K–$2.8M per MW today, on a path to $1.0–2.8M in the Kyber era. The L8b/L8c power-semi layers capture $50K–$150K per MW combined. The ratio compounds against the silicon layer in the Kyber era because cooling and 800V busway content scales faster than chip count. The chip-to-grid value chain's dollar-weighted center of mass sits at G1–G4, not at L8b/L8c. ETN and VRT capture the money; TXN and NVTS capture the margin per dollar.

Read top-to-bottom: power plant to die. Bullish-accent boxes hold cohort longs; copper-accent boxes hold cohort shorts; muted boxes are watchlist or out-of-scope. Dashed edges mark the four binding chokepoints — at the silicon layer (CoWoS · EUV) and at the electrical layer (GOES · HFO refrigerants).

flowchart TB
  classDef long fill:#3a2e1a,stroke:#c8a04a,color:#fef3d6,font-family:'Geist Mono',font-size:11px
  classDef short fill:#3a1a18,stroke:#b85a3c,color:#fde0d8,font-family:'Geist Mono',font-size:11px
  classDef watch fill:#1c1f28,stroke:#5a6878,color:#cdd2da,font-family:'Geist Mono',font-size:10px
  classDef gap fill:#1a1a18,stroke:#4a4a48,stroke-dasharray:4 3,color:#aaaaa6,font-family:'Geist Mono',font-size:10px
  classDef anchor fill:#5a4218,stroke:#e8c46a,color:#fff5d8,font-family:'Geist Mono',font-weight:600,font-size:13px
  classDef chokepoint fill:#2e1614,stroke:#c2603e,color:#fde0d8,font-family:'Geist Mono',font-size:10px

  subgraph G ["Grid · Building · Rack — dollar-volume center of mass"]
    direction TB
    G0["G0 · Generation
SMR · gas · BESS · HVDC
out of scope"]:::gap
    G1["G1 · Site interface
switchgear · MV transformers · ATS
$500K–$2M /MW"]:::long
    G2["G2 · DC backbone
UPS · BBU · busway
$600K–$2.8M /MW"]:::long
    G2T["G2T · Cooling
CDU · cold plates · immersion
$300K–$700K /MW"]:::long
    G3["G3 · 800V transition
SST · PSU · supercaps
$200K–$500K /MW"]:::long
    G4["G4 · Rack power
PDU · busbar · power shelves
$150K–$400K /MW"]:::long
  end

  GOES["GOES chokepoint
128–144wk lead times
Cleveland-Cliffs sole US"]:::chokepoint
  HFO["HFO refrigerant
Honeywell + Chemours
>75% R1234ze"]:::chokepoint

  GOES -.gates.-> G1
  GOES -.gates.-> G2
  HFO -.gates.-> G2T

  ETNn((ETN)):::anchor
  VRTn((VRT)):::anchor

  G1 --- ETNn
  G1 --- VRTn
  G2 --- VRTn
  G2 --- ETNn
  G2T --- VRTn
  G3 --- ETNn
  G4 --- VRTn

  subgraph PS ["Power semis — margin per dollar"]
    direction TB
    L8a["L8a · SiC substrate
800V rectification
WOLF share 60% → 34%"]:::short
    L8b["L8b · GaN
800V→48V · 800V→6V
$50K–$150K /MW"]:::long
    L8c["L8c · Board power
VRM · BCM · eFuse · 48V→1V
$30K–$80K /MW"]:::long
  end

  WOLFn(("WOLF · short")):::short
  NVTSn((NVTS)):::anchor
  TXNn((TXN)):::anchor

  L8a --- WOLFn
  L8b --- NVTSn
  L8b --- TXNn
  L8c --- TXNn

  subgraph CHIP ["Chip stack — L7 down to materials"]
    direction TB
    L7["L7 · Networking
NVLink · IB · Tomahawk · CPO"]:::long
    L6["L6 · Compute
GPU · ASIC · CPU"]:::long
    L5["L5 · Advanced packaging
CoWoS · SoIC · EMIB · Foveros"]:::long
    L4["L4 · Memory
HBM · DRAM · NAND"]:::gap
    L3["L3 · Foundry
N3 · N2 · A16 · 18A · 14A"]:::long
    L2["L2 · EDA
Cadence · Synopsys"]:::gap
    L1["L1 · WFE / litho
EUV · etch · deposition · inspection"]:::gap
    L0["L0 · Materials
wafers · resist · gases · gallium"]:::gap
  end

  CoWoS["CoWoS-L chokepoint
NVDA ~60% allocation"]:::chokepoint
  EUV["EUV chokepoint
ASML sole-source"]:::chokepoint

  CoWoS -.gates.-> L5
  EUV -.gates.-> L1

  NVDAn((NVDA)):::anchor
  AVGOn((AVGO)):::anchor
  TSMn((TSM)):::anchor
  INTCn(("INTC · short")):::short

  L7 --- NVDAn
  L7 --- AVGOn
  L6 --- NVDAn
  L6 --- AVGOn
  L6 --- INTCn
  L5 --- TSMn
  L5 --- INTCn
  L3 --- TSMn
  L3 --- INTCn

  G --> PS
  PS --> CHIP
    

G1 · Site / utility interface — Eaton, Vertiv (UPS+ATS).

Switchgear, MV transformers, ATS. ETN's primary share-capture territory; VRT plays at the UPS+ATS subset. Q4 2025 ETN datacenter orders ~3× YoY; $19.6B record backlog. The binding constraint here is not demand — it is GOES (grain-oriented electrical steel) supply, with Cleveland-Cliffs as the sole US producer and 128–144-week lead times. Schneider's "2028–2030 real impact" framing is the physical reality of order-to-revenue conversion, not a demand-side hedge. → ETN

G2 · DC backbone — Vertiv, Eaton.

UPS, BBU, busway, distribution. The widest dollar-volume layer per MW. VRT Q4 2025 organic orders +152% YoY; backlog $15.0B at 2.9× book-to-bill. Management reportedly stopped disclosing quarterly orders/backlog because the numbers became "too extreme." Deferred revenue $1.8B (+71% YoY) confirms hyperscaler pre-payment for delivery slots. → VRT · → ETN

G2T · Cooling / thermal — three-player race by 2027.

Until March 2026, VRT held unchallenged ~22% CDU share. Two simultaneous M&A events changed the structure permanently: ETN closed Boyd Thermal ($9.5B, $1.7B revenue at 80%+ DC mix) and Ecolab acquired CoolIT ($4.75B). The market is now a credible three-player race entering the highest-demand window of the AI-DC cycle. VRT's cooling moat compressed from wide to narrow. Watch CDU bookings quarterly — a 5+ ppt VRT share loss over two consecutive quarters is the trim trigger.

G3 · 800V transition — first-to-market window.

SSTs, 800V HVDC PSUs, 800V busways, supercaps. VRT H2 2026 800V product portfolio launch is the first to market by 18–24 months versus Schneider's "real impact" 2028–2030 framing. Per-MW content uplift in the Kyber era is +70–120% for VRT and +100% for ETN (per Findings 8 + 11). Each rack moving from 100kW to 600kW–1MW is a revenue expansion event independent of share gains.

G4 · Rack / row power — Vertiv plus connector layer.

PDUs, busbars, power shelves, sidecar racks, HV connectors. VRT plays here directly; the connector layer (TE Connectivity, Amphenol, Aptiv, Rosenberger, BizLink) and protection (Littelfuse) are watchlist exposure. Delta Electronics (overtook Foxconn by Taiwan market cap in January 2026) is the cleanest Taiwan-listed PSU consolidator and is on the bench.

L8a · SiC substrate — the cautionary tale.

Wolfspeed substrate share collapsed from >60% to ~34% over 36 months as Chinese competitors (TanKeBlue, SICC) gained scale. ST also flagged as adjacent. "Structural transitions do not guarantee equal outcomes" — synthesis Section 6. The cleanest paired long against WOLF is onsemi (ON), with Qorvo SiC JFET acquisition and AI-DC revenue >$250M in 2025, holding the SiC vertical-integration thesis with strengthening competitive position. → WOLF

L8b · GaN — four-way race, not three.

The prior synthesis's three-way frame (Infineon scale / TI vertical / Navitas density) was incomplete. Innoscience runs 8" GaN-on-Si IDM at scale, has ~30% global GaN share (#1 globally), and is the sole Chinese partner on NVIDIA's 800VDC list. The correct frame is four-way: Innoscience ~30% (cost-floor risk) · NVTS ~17% (density bet, GaN-IC patent estate) · POWI ~17% · EPC ~12–15% · IFX ~10% (scale, 300mm) · TXN ~5–7% (system-BOM bet, not device-share). April 2 2026 ITC FD in Infineon v. Innoscience is the dated GaN-IP regime catalyst. → NVTS · → TXN

L8c · Board power — TXN's vertical integration hunting ground.

VRM, BCM, eFuses, hot-swap, sequencing, supervisory analog. MPWR holds ~70% of NVIDIA Vera Rubin VRM share at the peak socket; TXN's bet is system-BOM capture at the surrounding 1,500+ analog SKUs per rack at TI's 58% gross margins. TI's NVIDIA GTC March 2026 silicon-anchor partnership names TI exclusively at the silicon-anchor tier (97.6% efficiency, >2,000W/in³). → TXN

L7 + L6 · Compute and networking — NVDA, AVGO; INTC short.

NVIDIA holds ~60% of TSMC CoWoS-L allocation through 2027 and ~70% of SK Hynix HBM4 for Vera Rubin. AVGO captures margin on every hyperscaler ASIC (TPUv7, Trainium3, MTIA, OpenAI 2027 chip) plus Tomahawk scale-out. The custom-silicon counter-leverage caps NVDA's hyperscaler pricing power but does not displace it on integrated cluster-class problems. INTC is the foundry pivot bet — binary on 14A. → NVDA · → AVGO · → INTC

L5 + L3 · Foundry and packaging — TSM is the binding chokepoint.

TSMC owns ~90% leading-edge logic; CoWoS-L is the binding AI-shipment chokepoint. Advanced packaging is now the new process — cost per transistor flat since N7 and rising at N2/A16; density comes from CoWoS, SoIC, EMIB, Foveros, hybrid bonding. Hybrid bonding tools (BESI, AMAT, Shibaura) are themselves a chokepoint. → TSM

L4 · Memory — uncovered cohort gap.

SK Hynix >50% HBM bits; HBM4 ramping into Rubin / MI450X / TPUv7 with bus doubled to 2048 bits. Memory is Bottleneck #2 in the three-bottleneck frame. SK Hynix is the highest-priority next deep-dive add to close this gap.

L1 · WFE / litho — uncovered cohort gap.

ASML is "the only irreplaceable company in chips." Conviction 5 in prior watchlist; not promoted to deep-dive only because the analyst budget went to chip-to-grid expansion. High-NA EUV adoption decisions at TSMC and Samsung in 2026 are the next live inflection. ASML is the top single completion candidate for next deep-dive cycle.