§ 01Executive View
TSMC plays in three concentric markets — global pure-play foundry (~$165–200B in 2026), leading-edge logic (≤5nm, the structurally tightest sub-segment), and advanced packaging (CoWoS/SoIC, ~$49–55B and the actual binding constraint on AI shipments). It commands ~64–70% of the pure-play foundry market overall and ~85–90%+ at the leading edge, sitting inside a 3-player oligopoly (with Samsung Foundry ~7% and Intel Foundry <1%) that is functionally a monopoly at N3/N2. The cycle is mid-AI-supercycle on the upswing, with Q4'25 IDC prints showing the foundry market in a recovery-to-expansion phase, structural pricing power demonstrably real (4 consecutive years of advanced-node price hikes announced for 2026–2029), and the company sitting on the share-gainer side of every market-shape vector that matters.
§ 02Market Sizing
| Market | TAM | SAM | SOM (TSMC share) | Source |
|---|---|---|---|---|
| Global pure-play foundry (2026) | $167–202B (consensus ~$180B) | ~$170B (TSMC's served geo/product footprint is essentially the entire market ex-China-domestic) | ~$122.5B revenue / ~64–70% share | GMI, Fortune Business Insights, Mordor, Counterpoint |
| Leading-edge logic (≤5nm, 2026) | ~$95–110B (estimated as the leading-edge slice of pure-play) | ~$95B (TSMC + Samsung + Intel addressable) | ~85–90%+ share at N5/N3, >90% at N2 | PatentPC, Counterpoint, FinancialContent |
| Advanced packaging (CoWoS/SoIC/InFO, 2026) | ~$49–55B by 2026 (broader advanced packaging including OSAT competitors) | ~$25–30B for high-density 2.5D/3D (CoWoS-class) | ~85%+ of CoWoS-L wafer capacity (~120–130K WPM by EOY26 vs ~35K WPM late-24) | SemiWiki, Astute Group, FinancialContent |
| Foundry 2.0 (IDC definition: foundry + packaging + test + masks) | ~$330B in 2025 with 11% YoY growth | ~$330B | 37–39% (IDC) | IDC, Electronics For You |
| Discrepancies flagged | GMI ($180B) vs Fortune ($202B) for 2026 differ by ~12% — within tolerance. Mordor's $58.9B 2023 base figure conflicts sharply with Counterpoint's pure-foundry numbers — reflects different methodology (Mordor likely excludes TSMC capacity outside taped-out wafer revenue; treat their CAGR figures with caution). The "Foundry 2.0" expansion (37–39% TSMC share) is IDC's broader definition and not directly comparable to the ~64–70% pure-foundry share number. Use pure-play numbers as the operative TAM. |
The most reliable single figure: TSMC's 2025 foundry revenue was ~$122.5B, +36% YoY, equating to ~64–70% of pure-foundry and ~85–90% of leading-edge. Counterpoint Q3'25 prints TSMC at ~71% share gaining vs Samsung at ~6.8% losing.
§ 03Growth Quality
The market's 2024–2030 CAGR consensus clusters around 7.5–9.1% for total foundry, but this is misleadingly low — the leading-edge sub-segment is forecast at ~28% CAGR (10/7/5nm-and-below tier). 3nm is highest-CAGR within that.
Decomposing TSMC's growth:
- Volume growth (~50–60% of 2025–2026 revenue uplift): wafer starts expanding at N3/N5/N2 + CoWoS doubling (35K → 130K WPM). Real units, real customers, real backlog.
- Price growth (~15–20% of uplift): 2nm wafers priced ~50% above 3nm (~$30K vs ~$20K), and TSMC has notified customers of price hikes for four consecutive years starting 2026 at 5–10% on advanced nodes. This is uncommon ASP discipline; in foundry history, ASPs typically deflated as nodes matured. TSMC has broken that pattern.
- Mix shift (~15% of uplift): the leading-edge mix (N5+N3+N2) is rising as a % of total revenue, lifting blended ASPs and gross margins. Apple/Nvidia/AMD/Broadcom anchor pre-payment financing for new nodes.
- New segment / geography: Arizona Fab 21 (N4 production, N3 / N2 ramping), Japan JASM (mature), Germany (announced, mature). Geographic diversification is a cost story (Arizona ~30% premium) and a customer-trust story, not a TAM expansion story per se.
- Cycle recovery: H2'24–2025 was the trough of the post-pandemic foundry inventory cycle for non-AI customers (auto, mobile, consumer); H2'25 is the recovery phase. AI demand never cycled down.
5y CAGR (2025–2030): 7.5–9.1% blended foundry; 25–28% leading-edge. 10y CAGR (2025–2035): GMI projects ~5.6%; this likely understates given AI structural demand. Fair-range estimate: 6–8%.
The company's own narrative (CC Wei: HPC growing 40% CAGR mid-decade, AI accelerator silicon doubling annually) is more aggressive than third-party consensus. Where the company stretches consensus: AI accelerator wafer-equivalent unit growth. Where consensus stretches the company: trailing-edge growth (mature nodes) — auto, IoT, and consumer logic at N7+ are softer than vendor reports imply.
§ 04Cycle Position
Phase: mid (early-to-mid for AI-driven leading-edge; mid-to-late for trailing-edge consumer/auto) Inventory cycle: recovery transitioning to expansion (Q4'25–H1'26)
The semiconductor industry is mid-supercycle, not late. IDC, Deloitte, and SemiAnalysis frame 2026 as the year the global semis market crosses $975B–$1T in annual sales for the first time, with 26% YoY growth in 2026. The notable structural fact: hyperscale buyers have signed long-dated supply agreements (3–5 year capacity reservations at TSMC, including pre-payments) that historically did not exist in foundry — these absorb the inventory volatility that historically broke chip cycles. As one analyst frames it, "AI demand has permanently rewired semiconductor pricing."
For TSMC specifically, the cycle position has three layers:
- Leading edge (N5/N3/N2): early-mid cycle. N2 just entered HVM Q4'25 with >65% yields. A16 ramps H2'26 with backside power. The classic "first 18–24 months of a node = peak ASP, peak share" window is firmly active.
- CoWoS/advanced packaging: early-cycle. The market is in capacity-constrained build-out — Nvidia has locked 60% of 2026 wafers; Broadcom 15%; AMD 11%. >85% of capacity is pre-allocated. Pricing power is at the highest point in any sub-segment of the entire semiconductor stack.
- Trailing edge (N7 and older): mid-to-late cycle. Auto inventory mostly cleared; mobile flat; consumer slow recovery. This is also where Chinese capacity (SMIC, HuaHong, Nexchip) is growing fastest and adding deflationary pressure on global trailing-edge ASPs (UMC, GlobalFoundries, VIS, PSMC are the casualties — TSMC mostly insulated).
The single most important cycle-level fact: the inventory bullwhip that historically breaks foundry cycles has been muted by hyperscaler long-dated reservations, and AI accelerator demand is a flow that continues to accelerate, not a stock to be digested.
§ 05Pricing & ASP
ASP trend: rising, with structural durability.
Drivers:
- N2 priced ~50% above N3 at ~$30K/wafer vs ~$20K. This is the largest node-over-node ASP step-up in TSMC's history.
- Advanced node price hikes 5–10% in 2026, continuing for 4 consecutive years (2026–2029) per Digitimes/TrendForce. Single-digit increases on N3/N4/N5/N7; 10–20% on N2.
- CoWoS-L pricing is its own ASP layer — high-density advanced packaging adds significant per-wafer-equivalent revenue on top of front-end wafer revenue. Effective AI-die ASP (logic + HBM base + CoWoS-L + InFO) is substantially higher than the front-end wafer alone.
- Mix shift to leading-edge inside TSMC's revenue mix is itself a durable ASP-rising lever.
TSMC's pricing position vs. market: TSMC is the price-setter at the leading edge, full stop. Samsung Foundry is forced to price 15–25% below TSMC at equivalent nodes to win even small wins (Tesla AI6, IBM, partial Qualcomm), and yield gaps make Samsung's effective economics worse than the headline discount. Intel Foundry has no leading-edge external pricing to compare yet (18A revenue $223M Q3'25, ~0.5% of global). At trailing edge, TSMC is somewhere in the middle of the price band — UMC, GlobalFoundries, VIS compete directly; SMIC undercuts on price-aware Chinese demand.
The deeper point: TSMC's pricing power at the leading edge is not merely durable; it is increasing. A foundry pushing prices up four years in a row, with customers who pre-pay, in a market where the only competitive alternative is yielding poorly — that is monopoly economics expressed politely.
§ 06Market Structure
| Metric | Value |
|---|---|
| Credible competitors at leading edge (≤5nm, 2026) | 3 (TSMC, Samsung Foundry, Intel Foundry) — functionally 1.x given Samsung yield issues and Intel's pre-revenue status at 18A |
| Top-3 share concentration (pure-foundry, Q3'25) | TSMC ~71% + Samsung ~6.8% + SMIC ~5.5% ≈ ~83% |
| Top-3 share at leading edge (≤5nm) | TSMC ~85–90% + Samsung ~8–12% + Intel <2% ≈ ~98%+ |
| Approx. HHI (pure foundry) | ~5,200 (TSMC alone contributes ~5,041) — highly concentrated; threshold for "high concentration" is 2,500 |
| Approx. HHI (leading edge) | ~7,500–8,200 — near-monopoly |
| Barrier-to-entry trend | Rising. Capex per leading-edge fab now $20–40B; EUV scanners $200M+ each, High-NA $400M+; ecosystem (PDK + IP + EDA + customer trust) requires decades to build. Rapidus is the live test — user is openly skeptical it succeeds. China's parallel stack is regional, not global. |
| Switching costs (customer-side) | Extremely high. PDK-coupled designs cost $50–500M+ to redesign for a different foundry. Apple/Nvidia/Broadcom/AMD have never moved a leading-node design off TSMC. |
| New entrant horizon | Effectively zero. Rapidus 2nm risk production 2027 is the only credible new entrant attempt; GlobalFoundries exited the leading-edge race in 2018. China's SMIC is structurally walled out by EUV export controls. |
This is among the most concentrated markets in any industrial sector globally — comparable in HHI to ASML's EUV monopoly or De Beers diamond at peak, more concentrated than Boeing/Airbus or Visa/Mastercard.
§ 07Disruption Watch
Primary disruption vector: chiplet/UCIe ecosystem standardization could compress integration moat — but compression is not the same as collapse.
The thesis: as UCIe matures (120+ consortium members, mainstream 2026 adoption), the ability to mix dies from different foundries inside a single package goes up. In principle, this lets a hyperscaler put a TSMC N2 compute die next to a Samsung HBM base die next to an Intel I/O chiplet, integrated by a third-party OSAT. In principle, that erodes TSMC's "everything in one place" advantage.
In practice: (1) TSMC's CoWoS-L is the binding constraint, not the substrate fabric, and TSMC has scaled CoWoS faster than ASE/Amkor can match; (2) hyperscalers have actually responded to UCIe by reserving more TSMC packaging capacity, not less — Nvidia 60% of 2026 capacity, AMD 11%, Broadcom 15%; (3) the integration tax for true multi-foundry packages (timing closure, thermal, signal integrity at >32 Gbps UCIe lanes) remains material. The strategic advantage has shifted from lithography to packaging — and TSMC happens to lead in both. So UCIe is a real long-term threat, but TSMC has structurally captured the new battleground.
Secondary disruption vectors (lower likelihood, longer horizon):
- Photonic interposers / on-die optics (Lightmatter, Celestial AI, Ayar Labs, late 2020s): could change the packaging ASP layer, but TSMC is the natural process partner for all of them.
- Intel 14A with DSA (2027 target, binary): if 14A's directed self-assembly works at yield, Intel re-enters the leading-edge competitive set. User is openly skeptical. Even if it works, ecosystem (PDK, IP, customer trust) is a 5+ year rebuild.
- Geopolitical tail (Taiwan invasion / blockade): structurally existential for the thesis, not for the market (the market collapses too — there is no Plan B for 18+ months globally). This is a portfolio-construction issue, not a market-structure issue.
- Custom silicon at hyperscalers: zero foundry-level disruption. Every hyperscaler ASIC (TPUv7, MI450X, Trainium3, Maia 2, OpenAI/Broadcom 2027 chip) is fabricated at TSMC. Custom silicon is a Nvidia disruption vector, not a TSMC disruption vector. TSMC wins regardless of which accelerator brand wins.
Likelihood of meaningful structural disruption in 5-year horizon: low (~15–20%). Likelihood in 10-year horizon: moderate (~35–40%) — primarily through chiplet-ecosystem maturation reducing TSMC's incremental share gains, not collapsing its base.
§ 08Bull Points
- Functional monopoly at leading edge with rising pricing power. ~85–90%+ share at N3/N2; first-time-in-history four-year ASP hike runway 2026–2029. HHI in leading-edge logic is ~7,500–8,200 — near-monopoly territory. There is no precedent in any industrial sector for a company holding this share at this growth rate at this margin profile losing share in <5 years absent a Black Swan.
- CoWoS is the binding AI constraint, and TSMC is the constraint. Nvidia/AMD/Broadcom are Nvidia/AMD/Broadcom-supply-constrained-by-TSMC. With CoWoS doubling 35K → 130K WPM by EOY26 and >85% pre-allocated, TSMC captures the AI bottleneck rent in the most mechanically certain way in the entire stack.
- Customer pre-payment funds expansion at zero capital cost. Apple's pre-pay-per-node and hyperscaler long-dated reservations effectively make TSMC's customers underwrite its capex. This is structurally rare — most capital-intensive industries fund their own expansion.
- TAM is rising at the leading-edge sub-segment at ~25–28% CAGR, and TSMC's share of that fast-growing slice is also rising. Both vectors of growth math (TAM × share) are positive.
- The cycle has been rewired by hyperscale long-dated commitments, dampening the historical foundry cycle volatility that has historically broken upcycles in 18–24 month bullwhips.
§ 09Bear Points
- Taiwan geopolitical tail. Single most concentrated geographic risk in global tech. A blockade or invasion would render the thesis (and most of the AI infrastructure thesis) inoperable for 18+ months. Arizona/Japan/Germany are partial mitigations but ramp slowly and at ~30% cost premium.
- Cost-per-transistor flatlining since N7, rising at N2/A16. The Moore's Law deflation that historically drove customer-volume growth is over. Future TAM expansion increasingly relies on ASP (which TSMC controls) and on advanced packaging (which TSMC also controls) rather than unit-cost-driven adoption. This is a multi-year tailwind for now, but eventually customers' ability to pass through silicon cost increases is bounded.
- Capex intensity is structurally higher each generation. $20–40B per leading-edge fab; High-NA EUV at $400M+ per scanner. ROIC on each new node is mathematically harder to maintain even at ASP increases, especially with Arizona/Japan/Germany cost premiums layered in.
- Trailing-edge competitive pressure from China. SMIC + HuaHong + Nexchip are growing trailing-node share aggressively, with state subsidies. TSMC's mature-node business is exposed to ASP deflation here over 3–5 years — not catastrophic given mix toward leading edge, but a real margin headwind.
- Chiplet/UCIe long-tail erosion of integration moat. Probability low in 5y, but real over 10y — TSMC's "everything-in-one-house" advantage gradually decomposes as packaging standards mature.
§ 10Conviction (1–5)
5 / 5
Highest possible market-positioning conviction. This is among the cleanest market-shape long cases in the entire investable universe of public equities. Every market-level vector (TAM growth, share trajectory, ASP trend, cycle position, structural concentration, barrier-to-entry trend, customer captivity) is positive. The only meaningful downside risk is geopolitical and is entirely exogenous to market shape. Where the conviction is not 5: timing of entry (cycle is mid, not early — there is some possibility of a 2027 digestion period if AI capex pauses) and absolute valuation (out of scope for this lens). On market positioning specifically, this is the rarest of cases — a near-monopoly in a structurally accelerating market with rising pricing power.
§ 11Key Risks to This Read
- Taiwan tail is the dominant non-market risk and dwarfs every other consideration. This memo treats the market as ongoing — the geopolitical scenario where the market itself is destabilized is a portfolio-construction question, not a market-shape question.
- AI capex digestion in 2027. If hyperscaler 2026 capex (~$600B) does pull forward demand and a 6–12 month pause materializes in 2027, TSMC's near-term growth narrative softens. Cycle position is mid, not early, and the most likely timing-related drawdown vector is a 2027 pause rather than a structural problem.
- Cost-per-transistor flatline. The unit-cost-of-intelligence narrative (per the synthesis) requires some mechanism of compute-cost compression to keep pulling demand in. If that mechanism shifts permanently from process shrinks to architecture (MoE, FP4, MLA), the volume tailwind for foundries decelerates relative to consensus models.
- Chinese parallel-stack scale beyond CloudMatrix 384. SMIC + Huawei + CXMT are walled out at HBM and EUV today. If China successfully closes either gap (low probability, multi-year), TSMC's trailing-edge share erodes faster.
- Methodology distrust on TAM. Sizing reports range from $167B to $202B for 2026 foundry — within tolerance but a reminder that vendor-published TAMs round upward. Use ~$180B as the operative central estimate and triangulate against TSMC's own revenue (~$122.5B in 2025) for share math.
§ 12Sources
- Counterpoint Research, "Global Pure Foundry Market Share: Quarterly" — pure-foundry share data, Q3'25 prints
- IDC, "Semiconductor Foundry 2.0 Market is Entering the Growth Phase" — Foundry 2.0 sizing, 11% YoY growth 2025
- Global Market Insights, Fortune Business Insights, Mordor Intelligence — TAM 2026 estimates ($167–202B range)
- TrendForce, Digitimes, Wccftech — TSMC 2nm pricing (~$30K), four-year price-hike runway 2026–2029
- SemiWiki, FinancialContent, Astute Group — CoWoS capacity scaling (35K → 130K WPM), Nvidia 60% / Broadcom 15% / AMD 11% allocation
- PatentPC, FinancialContent — TSMC vs. Samsung vs. Intel competitive positioning, Q3'25 share data
- Deloitte 2026 Outlook, Fabricated Knowledge (Doug O'Laughlin), 24/7 Wall St — semiconductor cycle 2026, "$975B / $1T market", "AI permanently rewired pricing"
- Tom's Hardware — "giga cycle" framing
- TSMC 2024 Annual Report
- Synthesis ("The Semiconductor Industry: A Beginner's Companion", "The AI Power Crisis Parts 1 & 2") — value chain context
- Cohort
companies.jsonTSM entry — supporting quotes, catalysts, risks
Works cited
- TSMC Q4 2025 Earnings Call Transcript
- Q4 2025 GM 62.3% above 59-61% guide; FY2025 GM 59.9% +380bps YoY; FY2026 GM guide 63-65%; pricing 'strategic, not opportunistic'
- Counterpoint Global Pure Foundry Market Share Quarterly
- Quarterly share series TSMC/Samsung/SMIC; Intel Foundry 6% in Foundry 2.0 frame
- Samsung 2nm Yields ~55%, Below MP Threshold (TrendForce, Apr 2026)
- Samsung 2nm yield ~55% as of April 2026, below ~60% MP threshold; Qualcomm leaning back to TSMC
- Samsung Lands $17B Tesla AI6 Foundry Deal (TrendForce)
- Tesla AI6 $16.5-17B Samsung Foundry win at Taylor TX; first major external 2nm-class commitment for Samsung in years
- Samsung vs TSMC vs Intel Foundry Market Numbers (PatentPC)
- Q3 2024 baseline TSMC 64.9% / Samsung 9.3%; Samsung dual-role IDM/foundry conflict; customer-flight pattern
- TrendForce 2Q25 Foundry Revenue 14.6% Up, TSMC 70%
- TSMC Q2 2025 share 70.2%, revenue $30.24B
- TSMC 2nm 50K to 140K Wafers in 2026 Supply Shock (StreetStocker)
- N2 capacity ramp 40k -> 100k wafer/mo 2026, 200k by 2027; demand exceeds initial ramp
- TSMC 2nm Up 10-20%, 3-7nm Single-Digit Hikes 2026 (TrendForce)
- N2 wafer ~$30k +10-20% above N3; N3-N7 single-digit hikes 2026
- TSMC CoWoS-L/S Fully Booked, OSAT Partners Step Up (TrendForce)
- CoWoS-L/S sold out; ASE CoWoP / Amkor stepping up as overflow OSAT alternatives
- TSMC Q4 FY 2025 Results and FY 2026 Outlook (Futurum)
- Q4 2025 GM and FY2026 guidance commentary; 56%+ long-term GM target reaffirmed
- TSMC Samsung Intel Who's Leading the Semiconductor Race (PatentPC)
- Qualcomm 8 Gen 1 35% Samsung yield vs 70% TSMC 4nm; subsequent migration to TSMC for all flagship Snapdragons
- China to Increase Leading-Edge Output 5x in Two Years (Tom's Hardware)
- China 7nm/5nm capacity targets - 100k wafer/mo by 2027-28, 500k by 2030; SMIC 7nm yield 60-70%
- Intel CEO Embraces 18A for External Customers (Tom's Hardware)
- Intel 18A external engagement; CFO acknowledged committed external 18A volume 'not significant' as of mid-2025
- Intel Foundry Reportedly Secures 18A for Microsoft Maia 3 (TechPowerUp)
- Microsoft Maia 2/3 anchor commitment to Intel 18A/18A-P
- Intel Going Big Time Into 14A - Lip-Bu Tan (Tom's Hardware)
- Intel 14A PDK distribution; two test-chip evaluators on Q4 2025 call; zero firm 14A external commitments
- NVIDIA Alone Has TSMC Advanced Packaging Booked Years Ahead
- NVIDIA wafer / advanced-packaging book through 2027
- Rapidus Lands $1.7B to Chase 2nm by 2027 (The Register)
- Rapidus $1.7B Feb 2026 tranche; IBM tech transfer; Tenstorrent first announced customer; 2nm risk production target 2027
- Samsung Hits 70% Yield on 2nm GAA SF2P (FinancialContent, Jan 2026)
- Samsung SF2P 70% yield headline (contradicted by April 2026 reporting); first credible 2nm second-source signal
- SMIC On Track to Produce 5nm for Huawei (Tom's Hardware)
- SMIC 5nm pilot 2026 for Huawei Ascend / Alibaba; DUV-only constraint
- TSMC Boosts CoWoS, NVIDIA Dominates Advanced Packaging Through 2027
- CoWoS scaling 35k -> 130k wafer/mo by end-2026; NVIDIA >50% allocation through 2027; 510k CoWoS-L wafers booked for Rubin/Vera/GB100
- TSMC Nears 70% Foundry Share, Gap with Samsung 62.7 pp (BigGo)
- TSMC ~70% pure-play foundry share 2025; gap to Samsung widened to 62.7 pp
- TSMC Q1 2026 Revenue and 66.2% Gross Margin
- Q1 2026 GM 66.2% above 63-65% guide; demonstrates active pricing power
- TSMC to Raise Advanced Node Quotes Up to 10% in 2026 (Tom's Hardware)
- 5-10% sub-5nm hikes 2026; Arizona ~15% premium, N5/N4 25% premium uniformly applied
- TSMC to Raise Prices for Four Consecutive Years From 2026 (WCCFTech)
- Customers notified of 4-year consecutive price hike cycle on advanced nodes
- Why TSMC Grew 4x Faster Than Foundry Rivals in 2025 (Tom's Hardware)
- TSMC growth rate vs rivals; price hikes + vertical integration + technology lead synthesis
- 24/7 Wall St - AI Demand Has Permanently Rewired Semiconductor Pricing
- Hyperscaler long-dated supply commitments dampening foundry inventory cycle
- Astute Group - Advanced Packaging Demand Soars: Nvidia Secures 60% of CoWoS
- Advanced packaging market sizing $49-55B by 2026
- CoWoS allocation
- BIS December 2, 2024 HBM Rule
- HBM density caps for PRC consumption
- bears on TSMC base-die packaging for restricted parties
- BIS Entity List actions and license-suspension notices re: Sophgo (late 2024)
- Underlying enforcement actions tied to Sophgo/Huawei Bingchuan-chip incident
- BIS October 17, 2023 export control rule update
- Expanded thresholds and entity scope
- further constrains TSMC PRC AI book
- BIS October 7, 2022 export control rule (advanced computing and SME to PRC)
- Foundation of FDPR sub-7nm restrictions binding TSMC for PRC fabless customers
- BIS press release — Commerce Strengthens Export Controls (Dec 2024)
- Dec 2024 SME / HBM rule scope
- BIS press release — Foreign-Owned Fab Loophole Closed
- Foreign-owned fab perimeter expansion
- Cohort companies.json (TSM entry id=2)
- Supporting quotes, catalysts (N2 ramp, A16, CoWoS doubling), risks (Taiwan geopolitical concentration, Arizona ~30% cost premium, capex/transistor flatlining)
- cohort companies.json — TSM entry (id 2)
- Customer concentration framing
- CoWoS as binding constraint quote
- catalysts and risks
- Cohort synthesis (chokepoint thesis, hyperscaler $600B capex, CoWoS bottleneck)
- Reverse DCF anchor: AI-cycle structural growth assumptions, CoWoS-L as binding constraint, Arizona 30% cost premium framing
- Cohort synthesis and ledger
- Context on export-control framing and Taiwan tail risk per user notes
- Cohort synthesis.md
- TSM macro positioning, Taiwan tail framing as 'existential', three-bottleneck thesis, AI capex aggregate (~$600B / 50 GW), FX cohort context, cyclicality framing
- cohort synthesis.md — Sections 2, 3.4, 3.7, 5, 7
- Value chain map, three-bottleneck framing, custom-silicon dynamics, hyperscaler $600B capex, end-market context
- Commerce CHIPS Program Office — Preliminary Memorandum of Terms with TSMC Arizona
- $6.6B direct funding
- capacity covenants
- clawback and PRC-expansion guardrails
- Coordination handoff with regulatory-analyst (BIS rule mechanics, CHIPS Act, FDPR)
- Macro lane covers trade-flow direction and FX consequences
- regulatory lane owns specific rule mechanics. Avoid double-counting per contract.
- Counterpoint Research - Global Pure Foundry Market Share Quarterly
- Pure-play foundry quarterly share by player
- Q3'25 prints (TSMC ~71%, Samsung ~6.8%)
- HHI inputs
- Covington & Burling — US Strengthens Export Controls on Advanced Computing and SME (Dec 2024)
- Legal-analysis perspective on Dec 2024 rules
- CRS — U.S. Export Controls and China: Advanced Semiconductors (Aug 2025)
- Export-control regime trajectory and TSMC China-customer revenue exposure
- Deloitte Insights - 2026 Semiconductor Industry Outlook
- $975B-$1T market 2026 sizing
- 26% YoY growth
- Digitimes - TSMC unveils four-year price hike for advanced chips starting 2026
- Four-consecutive-year ASP runway 2026-2029
- ASP discipline thesis
- Entropy Capital — ASML's Supply Chain, Bill of Materials
- ASML BOM and tier-2 dependency map
- Epoch AI — Advanced packaging and HBM, not logic dies, were the bottlenecks on AI chip production in 2025
- CoWoS-as-binding-constraint corroboration
- EU Commission State aid Decision SA.107536 — Germany — ESMC Dresden
- EUR 5.0B state-aid clearance for ESMC JV
- capacity and operations conditions
- Fabricated Knowledge (Doug O'Laughlin) - 2026 AI & Semiconductor Outlook
- Cycle framing - mid-supercycle, GB200 inventory partially resolved, expansion phase
- FinancialContent - High-Stakes Gamble: Intel Foundry Resurgence vs TSMC 2026
- Intel Foundry Q3'25 revenue ($223M, ~0.5%)
- Nvidia 18A pause
- competitive depth
- FinancialContent - The Great Packaging Pivot: TSMC Doubling CoWoS Capacity
- CoWoS allocation 2026 (Nvidia 60%, Broadcom 15%, AMD 11%, >85% pre-allocated)
- FinancialContent - The Silicon Mosaic: Chiplets and the UCIe Standard
- Disruption-watch on UCIe maturation
- 120+ consortium members
- mainstream 2026 adoption
- Fortune Business Insights - Semiconductor Foundry Market Forecast [2034]
- TAM 2026 estimate ($202B) - upper bound on consensus range
- GII Research / KSI - Semiconductor Foundry Market Forecasts 2025-2030
- 5y CAGR triangulation
- 10/7/5nm-and-below tier at 28.3% CAGR
- Global Market Insights - Semiconductor Foundry Market Size Growth Report 2035
- TAM 2026 estimate (~$180B)
- 5.6% 2024-2030 CAGR data point
- GuruFocus — TSM EV/EBITDA Historical (10y range)
- 10-year EV/EBITDA range (5.45 min / 9.26 median / 19.24 max) for historical context
- IDC - Semiconductor Foundry 2.0 Market Entering Growth Phase from Recovery (11% YoY 2025)
- Foundry 2.0 sizing
- recovery-to-expansion cycle phase
- TSMC 37% Foundry 2.0 share
- Industry supply-chain analyst estimates (TrendForce, SemiAnalysis, DIGITIMES) — cohort cross-references
- Top-10 customer composition estimate (Apple, NVIDIA, AMD, Qualcomm, MediaTek, Broadcom, Marvell, Sony, Intel, hyperscaler ASICs)
- estimated concentration percentages — flagged as estimates
- METI JASM Phase 1 (Dec 2021) and Phase 2 (Dec 2023) subsidy decisions
- JPY 476B and JPY 732B subsidy commitments to TSMC Kumamoto fabs
- Mordor Intelligence - Semiconductor Foundry Market Analysis
- TAM 2026 estimate ($184.78B)
- 7.42% CAGR 2025-2030
- Multiples.vc — TSMC Public Comps
- Cross-sectional valuation comparison vs WFE chokepoints (ASML, AMAT, KLAC) and foundry peers (UMC, GFS)
- PatentPC - TSMC, Samsung, Intel: Who's Leading the Semiconductor Race
- Leading-edge share at 3nm/2nm (TSMC 90%+)
- competitive positioning vs Samsung/Intel
- Public defense and strategic analyst commentary on Taiwan Strait scenarios
- Probability framing for blockade vs kinetic scenarios
- mechanism (PLA exclusion zone, fuel-reserve depletion, cable-cuts gray-zone). Probability bands are analyst judgment.
- Public macroeconomic regime references (FRED US 10y, DXY, USD/TWD spot, JPY/USD)
- Current regime: USD strength, US 10y 4-4.75% range, TWD weakness 2024-2026, JPY weakness 2022-2026
- Section 232 semiconductor investigation initiation notice
- Live investigation, statutory 270-day clock, presidential decision window
- Section 48D Advanced Manufacturing Investment Tax Credit — final regulations
- 25% ITC structure for TSMC Arizona qualified property
- SemiWiki - CoWoS Capacity Set to Skyrocket by 2026
- CoWoS capacity scaling 35K -> 130K WPM by EOY26
- 1M wafers demand by 2026
- Semiwiki - TSMC 2025 Update: Riding the AI Wave
- TSMC 2025 revenue (~$122.5B, +36% YoY)
- operational scale data
- SpecGas — Neon Production by Country 2026
- Post-2022 neon diversification (China-led, US/Korea capacity additions)
- StockAnalysis.com — GFS, UMC statistics pages
- GlobalFoundries (EV/EBITDA ~10.7x, fwd P/E ~22x) and UMC (EV/EBITDA ~5.5x, fwd P/E ~15x) for relative valuation
- StockAnalysis.com — TSM income statement / cash flow / balance sheet / statistics
- FY22-FY25 historical income / cash flow / balance sheet series
- current multiples (P/E 30.6x, fwd P/E 20.5x, EV/EBITDA 18.8x, EV/Sales 13.1x, FCF yield 1.9%)
- ROIC 52%, ROE 36%
- Taipower historical industrial rationing episodes (notably 2021 drought)
- Taiwan power and water as quasi-macro operating risk
- energy-import dependency context (~97% imported)
- fuel-reserve duration (~40 days)
- Taiwan Statute for Industrial Innovation Article 10-2 (Taiwan CHIPS Act)
- 25% R&D tax credit plus 5% advanced equipment credit
- effective-tax-rate floor
- TechSoda — Explainer: TSMC's 2024 Annual Report Highlights
- Annual report supplier-list synthesis
- Tom's Hardware - Semiconductor industry enters unprecedented giga cycle
- Giga-cycle structural framing of 2026 industry dynamics
- TrendForce - TSMC 2nm 60K Monthly Output 2026, Prices 50% Above 3nm
- N2 pricing premium (~50% above N3)
- 2nm capacity 60K WPM 2026
- TrendForce - TSMC 2nm Reportedly Up 10-20%; 3-7nm Single-Digit in 2026
- 2026 wafer pricing (N2 +10-20% over N3
- N3-N7 single-digit increases)
- Trendforce — ASML's Magic Uncovered: Tech and Partners Behind Its EUV Edge (Nov 2025)
- ZEISS / Cymer / TRUMPF tier-2 dependency mapping for ASML EUV
- Trendforce — Japan Ramps Up Photoresist Investment for 2nm Chips (Nov 2025)
- Photoresist supplier concentration, TOK Korea plant capex
- Trendforce — Japan Rumored to Curb Photoresist Exports (Dec 2025)
- Photoresist export-control geopolitical context
- Trendforce — Kioxia, TEL and Photoresist Makers in Focus After M7.7 Japan Earthquake (Apr 2026)
- April 2026 photoresist disruption stress-test data point
- Trendforce — TSMC Accelerates Arizona 2nd Fab, Eyes 3Q26 Tool Install (Dec 2025)
- Arizona Fab 2 timeline acceleration
- Trendforce — TSMC Reportedly Plans 12 New Advanced Process and Packaging Fabs in Taiwan (Nov 2025)
- Taiwan capacity concentration vs ex-Taiwan ramp
- Trendforce — TSMC Reportedly Pulls Arizona Third Fab to 2027 (Sep 2025)
- Geographic diversification ramp acceleration
- TSMC 1Q26 Management Report
- Q1 2026 P&L, segment mix (HPC 58%, smartphone 29%, advanced nodes 74% of wafer revenue), capex, cash balance
- TSMC 2024 Annual Report
- Tier-1 supplier disclosures, capex allocation, EUV scanner counts
- TSMC 2024 Responsible Supply Chain Report
- Continuity planning posture, 2,000+ chemical/material qualification, neon recycling
- TSMC 2025 Annual Report (English)
- FY25 segment mix, capital allocation framework, dividend policy, capex history
- TSMC 2025 SEC 20-F
- FY25 annual report regulatory filing for ADR
- cash flow detail
- SBC disclosure
- TSMC 4Q25 Earnings Call Transcript
- Capacity utilization, Arizona ramp commentary, capex guidance
- TSMC 4Q25 Management Report
- FY25 full-year P&L, capex (~NT$1.27T / ~$40B), balance sheet
- TSMC Arizona corporate site
- Arizona Fab 1 N4 HVM, yield parity statements
- TSMC Form 20-F (most recent annual filing)
- Customer concentration disclosure (one unnamed >10% customer), geographic/end-market revenue mix
- TSMC Form 20-F (most recent, FY2024)
- Risk factors, government grants disclosure, material litigation note
- TSMC FY24 Annual Report and 20-F filings (general reference)
- FX sensitivity rule-of-thumb (~40 bps GM per 1% TWD/USD move), revenue mix by geography, capex profile, segment mix HPC/smartphone/auto/IoT, balance sheet net cash position
- TSMC IR — Q1 2026 Quarterly Results page
- Q1 2026 revenue, gross/operating/net margins, capex, Q2 and full-year 2026 guidance
- TSMC Q1 2026 Earnings Call Transcript (Investing.com)
- Q1 2026 OCF (NT$699B), FCF (NT$348B), ROE (40.5%), raised long-term GM target (56%+), 2026 capex high-end of $52-56B range
- TSMC quarterly earnings calls (Q3 2024 through Q1 2026)
- HPC overtaking smartphone commentary, CoWoS capacity-doubling guidance, end-market segment color, demand-quality signaling
- TSMC quarterly earnings transcripts FY24-Q1 FY26 (general reference)
- Wafer pricing direction (2023 6-8% raise, 2024 ~3%, N2/A16 reported ~10-15% premium), China revenue trajectory, Arizona ramp commentary, water/power risk mentions
- User-provided cohort context for customer dimension
- Apple ~25%, HPC overtook smartphone in 2024–25, hyperscaler custom-silicon list, switching-cost description, cycle-position read by end-market
- USITC — Ukraine, Neon, and Semiconductors (executive briefing)
- Pre-2022 neon supply baseline
- Wccftech - TSMC Tight 2nm Supply, Four Consecutive Years of Price Hikes
- Confirms multi-year price-hike runway
- supply tightness at N2
- Wccftech — TSMC 2nm Tight Supply / Four-Consecutive-Year Price Increases
- Pass-through pricing power evidence
- Works in Progress Magazine — The world's most complex machine (ASML/EUV)
- ZEISS / Cymer / TRUMPF technical context