TSM / INTC

TSM Competitor competitor.md

TSMC is the rare case where competitive analysis can be written almost entirely in the negative space — there is no leading-edge logic competitor with viable share, and the only adjacent threats (Samsung Foundry, Intel Foundry, SMIC, Rapidus) are each fighting different battles, none of them at scale yet. TSMC's foundry market share reached ~70% by Q2/Q3 2025, with the gap to Samsung widening to 62.7 percentage points; on leading-edge AI logic the share is functionally ~90%+. The competitive posture is strongly long-supportive: pricing power is being actively exercised (Q1 2026 gross margin 66.2%, FY2026 price hikes 3–10% across nodes, four consecutive years of price hikes notified to customers), and the moat is strengthening — process leadership has been compounded by an advanced-packaging chokepoint (CoWoS-L) where NVIDIA alone has booked >50% of capacity through 2027. The single thing that could invalidate this read is non-competitive: Taiwan geopolitical disruption.

INTC Competitor competitor.md

Intel is structurally surrounded on every product line it sells, by competitors who either own better process (TSMC), better architecture (AMD), better software ecosystems (NVIDIA/CUDA), or better unit economics (ARM hyperscalers). The competitive read is short-supportive: Intel has lost meaningful share in every segment over the last five years, its moat is narrow and eroding, and the only credible path to widening it — Intel Foundry on 18A and 14A — requires winning customers from a TSMC ecosystem it does not currently match on PDK, IP, or yield. The Apple 18A entry-tier deal (Jan 2026), Microsoft, and the NVIDIA $5B equity stake (Dec 2025) are real datapoints, but external foundry revenue was still only $222M in Q1 2026 against $5.4B total foundry revenue — the optics are improving faster than the economics, and 14A with DSA remains the binary survival test the user already flagged.

TSM Supply chain supply-chain.md

TSMC's input side is structurally fragile in the abstract but operationally resilient in practice. The fragility is real: every leading-edge wafer the company ships requires equipment from a single Dutch firm (ASML), optics from a single German firm (ZEISS SMT, sole-sourcing ASML), photoresist from a Japanese trio whose advanced capacity is concentrated in Fukushima/Tohoku, and ~92% of the company's own production from one ~250-mile-long island that sits inside the most contested strait in the world. The resilience is also real: TSMC is the largest single counterparty for every one of those tier-1 suppliers, holds multi-year capacity allocations from them, qualifies redundant chemistry suppliers years in advance, recycles its own neon, and is now ~5 years into a credible (if slower-than-Taiwan) Arizona/Japan/Germany footprint diversification. For a long thesis, the question is not "can the supply chain break" but "what is priced into a 5–10% annual probability of a disruption that would take 12–24 months to recover from." I think the answer is: not enough, but the residual is paid for by the structural moat — TSMC is the only buyer who can actually absorb the tier-1 supply that exists, and that buyer power compounds.

INTC Supply chain supply-chain.md

Intel's supply chain is, paradoxically, the strongest leg of the short thesis to attack — and the weakest. Strongest because Intel's input-side risk is not a fragile-supplier story (the company is geographically diversified across the US, Israel, and Ireland; it has multi-year LTAs with ASML, AMAT, LAM, KLA, TEL, JSR, Shin-Etsu, SUMCO; it has actually secured ASML's first commercial High-NA EUV tool ahead of TSMC). Weakest because none of that solves the structural problem: Intel is internally its own most strained supplier. The bottleneck is 18A yield (still 7%/month curve, industry-standard not until 2027 per Tom's Hardware), packaging capacity that needs Amkor partnership to scale, and the humiliating fact that Intel itself is a customer of TSMC for the very tiles (Lunar Lake CPU, Arrow Lake GPU, Panther Lake GPU tile) that should validate IFS. That makes the short thesis here a capital-allocation short, not a supply-chain-fragility short — Intel can get the inputs, but cannot convert them to a product on time.

TSM Customer customer.md

TSMC has the strongest customer base in the entire semiconductor industry: every fabless leader at the leading edge is a customer, switching costs are measured in years and billions of dollars, and the customer mix is migrating to the highest-quality demand pool on Earth (HPC/AI). Concentration is real — Apple alone is roughly a quarter of revenue and the top ten customers cluster well above 70% — but the concentration is into the winners, not into a single fragile account, and HPC has now overtaken smartphone as the largest end-market, structurally lengthening the demand cycle. The customer dimension supports a high-conviction long: TSMC's customers are fighting each other for capacity, not negotiating it down.

INTC Customer customer.md

Intel's customer base is the structural weakness in the short. The product business is anchored by three OEM customers (Dell, Lenovo, HP) who buy a declining-volume, share-losing product (x86 client CPUs) into a late-cycle PC market — and a hyperscaler datacenter customer set that is actively diversifying away from x86 toward in-house ARM (Graviton, Axion, Cobalt) and AMD EPYC. The foundry "second customer base" — the entire bull thesis — is not yet a customer base: external foundry revenue ran ~$50M in mid-2025 against a ~$17.8B IFS segment, with one Microsoft chip and a few small DoD RAMP-C engagements as the only marquee names. That is press-release demand, not pull-through demand. In short, Intel's existing customers are eroding faster than its new customers are committing.

TSM Financial financial.md

TSMC is the highest-quality cyclical in the entire semi complex: 60%+ gross margins at peak, 50%+ operating margins, 50%+ ROIC, and a balance sheet that funds $50B+ of annual capex out of operating cash flow without ever touching the debt market in anger. The stock at ~$398 ADR / ~$1.75T market cap trades at ~20.5x forward earnings and ~13x EV/Sales — elevated vs its own history (10y EV/EBITDA range 5.4–19.2, currently 18.8) but the multiple is being supported by 30%+ revenue growth and structural margin expansion as AI/HPC mix dominates. The risk in the financials is not quality — it is the capital intensity step-change ($52–56B capex in 2026, ~43% of revenue) and whether the AI cycle compounds at the rate now embedded in consensus.

INTC Financial financial.md

Intel is a structurally impaired IDM with -$1.6B FY25 free cash flow, a still-loss-making foundry consuming ~$2.4B per quarter, $46.6B of debt, no dividend, and a ROIC of ~0.7% against a ~12.7% WACC — the textbook value-destruction profile. After a parabolic 129% YTD rally to ~$100/share, INTC now trades at ~$500B market cap, ~10x EV/Sales, ~38x EV/EBITDA TTM, and ~22x forward earnings on heroic 2026 numbers — multiples that put it inside TSMC territory while it generates fractionally better-than-zero margins on a flat revenue base. The market is pricing a successful 14A/18A foundry takeoff, gross margins reverting to 50%+, and external customer wins that have not yet materialized; if any one of those legs slips, the multiple compresses violently. This is a classic "narrative crowded into a still-broken P&L" short setup.

TSM Market positioning market.md

TSMC plays in three concentric markets — global pure-play foundry (~$165–200B in 2026), leading-edge logic (≤5nm, the structurally tightest sub-segment), and advanced packaging (CoWoS/SoIC, ~$49–55B and the actual binding constraint on AI shipments). It commands ~64–70% of the pure-play foundry market overall and ~85–90%+ at the leading edge, sitting inside a 3-player oligopoly (with Samsung Foundry ~7% and Intel Foundry <1%) that is functionally a monopoly at N3/N2. The cycle is mid-AI-supercycle on the upswing, with Q4'25 IDC prints showing the foundry market in a recovery-to-expansion phase, structural pricing power demonstrably real (4 consecutive years of advanced-node price hikes announced for 2026–2029), and the company sitting on the share-gainer side of every market-shape vector that matters.

INTC Market positioning market.md

Intel sits in the worst possible market-shape configuration: it competes in five distinct markets, none of which are simultaneously (a) growing structurally, (b) where Intel is the share leader gaining share, and (c) where Intel has clear product leadership. The two markets Intel still leads — PC client x86 and datacenter x86 — are losing share to AMD and being structurally reshaped by ARM at the same time the PC market is in a late-cycle pull-forward driven by Windows 10 EOL and the AI-PC narrative. The two markets where the bull case lives — pure-play foundry and merchant AI accelerators — are markets where Intel is a sub-1% share challenger entering markets shaped by entrenched 70%+ share leaders (TSMC, NVIDIA), with no clear path to a credible #2 position before 14A/2027–2028. The cyclical late-2025 inventory tightening in CPUs is masking the structural deterioration; on a 3-year view, share losses compound while every market Intel plays in is being reshaped by adjacencies it does not lead.

TSM Regulatory regulatory.md

Net regulatory posture is a modest tailwind on a 24-month horizon: TSMC is the single largest beneficiary of allied industrial policy (CHIPS Act ~$6.6B direct + ITC ~25%, METI JASM ~JPY 1.2T, EU Chips Act ESMC ~EUR 5B), and US/EU/Japan/Korea/Netherlands export controls structurally protect its position against SMIC. The single most material exposure is the Section 232 semiconductors investigation (Commerce, opened April 2025) — a finding could impose tariffs on Taiwan-fabbed wafers/packages entering the US, partially offset by Arizona ramp but materially adverse for the 2026–27 transition period when N2/A16 volume is concentrated in Hsinchu/Kaohsiung. The next dated catalyst worth tracking is the Section 232 final report deadline (270 days from initiation, mid-late 2026 window), and BIS Foreign Direct Product Rule (FDPR) enforcement actions following the Sophgo/Huawei "Bingchuan" chip incident.

INTC Regulatory regulatory.md

Intel is the single most regulatorily-cushioned name in US semis, and that cushion is the principal threat to a clean short. CHIPS Act direct funding (~$8.5B grants + up to $11B loans), DoD trusted-foundry programs (RAMP-C, SHIP, Secure Enclave), Section 232 domestic-fab tailwinds, and the live possibility of a Trump-administration federal equity stake or expanded loan guarantee form a meaningful floor under the equity that the operating fundamentals do not justify. The net regulatory read for a short is adverse: probability ~50–60% that some form of regulatory cushioning extends Intel's runway 12–24 months beyond what FCF alone implies, with offsetting downside vectors (BIS export controls capping China datacenter revenue, antitrust noise around subsidy disparity, securities-class-action overhang) that are real but smaller in magnitude than the federal lifeline optionality.

TSM Macro macro.md

TSM is a structural macro winner with a single, towering tail. In the modal world (95%+ probability over a 12-month horizon), the macro setup is favorable: USD-invoiced revenue against a TWD/JPY-skewed cost base means a strong dollar is a P&L tailwind, AI capex makes the company effectively counter-cyclical to traditional industrial weakness, and rate sensitivity is muted because capex is funded from operating cash flow. The dominant macro factor by an order of magnitude is geopolitical concentration in the Taiwan Strait: this is not "a risk among several," it is the only macro variable that can re-price TSM by 50%+ in a day, and it is the variable the rest of the world cannot model with confidence. Net read: structural macro tailwind in the body of the distribution, existential left tail.

INTC Macro macro.md

Intel is the cohort's most macro-fragile name on the short side. The dominant driver is rate sensitivity colliding with a capex super-cycle Intel can't pause — long-duration foundry cash flows discounted at higher rates, on top of a rising debt stack that must be refinanced into the front-end of the curve through 2028. Geopolitically, the US-domestic fab story (CHIPS Act, Arizona/Ohio) is real but mostly priced; the underpriced exposure is the Kiryat Gat (Israel) fab complex, which is a single-country tail that doesn't show up in cohort discussion. Net: a high-rate, strong-dollar, Pax-Americana regime is the worst possible backdrop for the bull case, and that is broadly where we are.

TSM Catalyst calendar thesis.md

INTC Catalyst calendar thesis.md

TSM Kill criteria

The thesis is invalidated if any of:

• Samsung SF2P yields hold at 70%+ for two consecutive quarters AND Qualcomm or AMD announces a >20% volume shift to Samsung 2nm by H2 2026. This breaks the customer-flight-is-one-directional axiom and re-prices the moat from "wide-strengthening" to "wide-eroding" — the worst long setup.
• TSMC FY26 gross margin compresses below 56% in any single quarter outside of an explicit Arizona-dilution-ramp explanation. The whole financial case rests on the long-term GM target raised to 56%+ as the structural floor; sustained breach signals pricing power has hit its ceiling and the four-year hike runway is being rolled back.
• Section 232 lands as a broad tariff without Arizona/anchor-customer exemption AND TSMC's Q3-Q4 2026 prints show <50% pass-through to customers. Modal outcome is priced; a punitive outcome with weak pass-through compresses operating margin 4–6 ppts and breaks the "pricing power absorbs everything" structural premise.
• Cross-strait posture escalates to declared blockade exercise or kinetic-precursor mobilization signal validated by USINDOPACOM-grade public statements. Position is closed regardless of conviction; this is a portfolio-protection trigger, not an analytical one.
• CoWoS-L capacity ramp slips by >25% on the 2026 exit (target ~130K WPM; floor ~98K WPM). The packaging chokepoint is the compounding leg of the moat; meaningful execution slippage signals the doubling can't be repeated and re-prices the AI-capture thesis.
• TSMC's reverse DCF requires >18% 10-year revenue CAGR to justify the price (vs current 13–15%). This would require either a meaningful price run with no earnings revision or a 2027 capex pause that compresses the forward growth path. Either way, the asymmetry breaks.

INTC Kill criteria

The thesis is invalidated if any of:

• A second brand-name fabless customer commits to 14A by Q1 2027 (Apple committing beyond entry-tier with a node leadership SKU; NVIDIA committing wafer volume rather than just co-design; AMD, Qualcomm, MediaTek, or Broadcom committing publicly). One Microsoft chip plus DoD RAMP-C is press-release-grade; two named brand-name fabless commitments at 14A is regime change.
• Federal equity injection or CHIPS covenant loosening is announced before Q3 2026 at terms that materially recapitalize the balance sheet (>$10B injection, multi-year covenant relief). This single regulatory event torpedoes the financing-stress timeline.
• Intel beats AMD's datacenter growth in three consecutive quarters (Q1'26 was the first such beat in 19 quarters per customer.md). One beat is cyclical pull-through; three beats is structural inflection that invalidates the customer-erosion leg.
• 18A external foundry revenue exceeds $1B/quarter run-rate by Q4 2026. Current run-rate is ~$222M/quarter (Q1'26). A 4x scaling is the threshold that converts "press-release demand" to "commitment demand" — not just a single-quarter spike but two consecutive quarters above the threshold.
• Gross margin expands above 42% GAAP for two consecutive quarters before end-2026. This is the line above which the structural pricing-power-loss thesis breaks and the recovery narrative validates.