Date: 2026-05-04 Conviction: 5/5 Sizing recommendation: 4.0–5.0% NAV (large; concentrated) Cohort role: Core
§ 01The thesis in 3 sentences
TSMC is a chokepoint-on-chokepoint monopoly: ~90% of leading-edge logic and ~85% of advanced AI packaging (CoWoS-L, 35K → 130K WPM by end-2026 with NVIDIA holding >50% of capacity pre-booked through 2027), producing Q1 2026 gross margin of 66.2% while raising its structural floor to 56%+ and executing four consecutive years of 5–10% advanced-node price hikes that customers accept because there is no alternative supplier at N3/N2. The business is self-funding $52–56B of 2026 capex from $73B+ FY25 operating cash flow with a $40B net cash balance, SBC at 0.03% of revenue, and ROIC ~52% — meaning reported earnings are real earnings and the capital cycle imposes no dilution risk. The only thing that breaks this thesis is Taiwan Strait posture: ~92% of advanced wafer capacity sits on a 35km strait, and that single uninsurable binary is the only reason the stock trades at a 10y-median-discounted multiple rather than at ASML-tier monopoly pricing.
§ 02Sizing rationale
Large (4.0–5.0% NAV) is warranted because all seven analysts converged long with the 4-conviction reads identifying the same root cause (full multiple + Taiwan tail), not independent concerns — concentrated residual risk is preferable to dispersed mid-conviction reads. The size is bounded at the top by cohort-level Taiwan correlation: NVDA, AVGO, and NVTS also carry significant Taiwan exposure, so the marginal Taiwan risk dollar at the portfolio level, not the standalone TSM conviction, sets the ceiling. Reserve 30% of target weight for a Section 232-driven or Taiwan-posture-driven drawdown; at ~$300 ADR (forward P/E ~15x), asymmetry shifts to approximately 3:1 and the correct response is to upsize, not reassess.
§ 03The 3 things that would make us wrong
- Samsung SF2P yields sustain at 70%+ for two consecutive quarters and Qualcomm or AMD publicly shift >20% of 2nm volume to Samsung — leading indicator: watch Qualcomm and AMD dual-track N2 qualification announcements; first print expected H2 2026.
- TSMC gross margin prints below 56% in any quarter outside an explicit Arizona-dilution explanation — leading indicator: quarterly gross margin disclosures; the structural floor has been raised once and a breach signals pricing power has peaked.
- Section 232 lands as a broad punitive tariff without an Arizona or anchor-customer exemption AND Q3–Q4 2026 prints show less than 50% pass-through to customers — leading indicator: Commerce final recommendation text (expected mid–late 2026); customer pricing disclosure in the same-quarter earnings.
§ 04The catalyst that proves us right
TSMC Q2 2026 earnings print (July 2026) showing gross margin at or above 66% with CoWoS-L ramp on schedule — this is the single most important near-term confirming signal because it simultaneously validates that the April 2026 M7.7 Japan quake (TOK Koriyama resist disruption) was absorbed with pricing pass-through intact, that the four-year hike cycle is holding, and that advanced packaging capacity is executing to the 130K WPM exit target. It confirms pricing power, supply-chain resilience, and moat compounding in one print — the three core pillars of the thesis.
§ 05Add / trim levels
- Add: 30% reserve deployed on any Section 232 adverse surprise drawing stock below ~$300 ADR (forward P/E ~15x); also add on any Taiwan-posture-driven drawdown not accompanied by kinetic escalation.
- Trim: If Samsung SF2P yields hold 70%+ for 2+ consecutive quarters AND a named customer announces >20% volume shift; or if FY26 gross margin falls below 56% in any quarter without explicit Arizona-ramp explanation.
- Cut: Cross-strait blockade exercise or kinetic-precursor signal validated by USINDOPACOM-grade public statements — full exit regardless of conviction; this is a portfolio-protection trigger.
§ 06Pair / hedge
TSM long / INTC short expresses foundry leadership as a relative-value position — see INTC thesis for the short leg. Note: Section 232 complicates this pair (a broad tariff could theoretically lift INTC's domestic-foundry narrative), so the cleaner expression is TSM standalone + INTC short sized as a probe. At the cohort level, TXN (~10–15% Taiwan exposure), ETN (minimal), and VRT (zero Taiwan production) provide a partial structural hedge against TSM's Taiwan concentration — this is the portfolio-level Taiwan discipline, not a name-level pair.
§ 07Why we hold this in a chip-to-grid cohort
TSM sits at L3/L5 in the chip-to-grid stack — it is simultaneously the leading-edge logic chokepoint and the advanced packaging chokepoint that every layer above it (NVDA accelerators, AVGO ASICs, HBM base-dies) depends on to reach production. Holding TSM as the core anchor of the cohort is holding the value chain's single most irreplaceable node: every dollar of AI-DC build eventually routes through a TSMC wafer or a CoWoS-L substrate.