Date: 2026-05-04 Conviction: 4/5 Sizing recommendation: 3.5–4.5% NAV (large; 40% of intended position held in reserve) Cohort role: Core
§ 01The thesis in 3 sentences
NVIDIA is the price-setter inside its own bottleneck — holding ~60% of TSMC CoWoS-L through 2027 and ~70% of SK Hynix HBM4 for Vera Rubin, generating $96.6B FCF at 60% operating margins, while trading at 23.8x forward P/E — below its 5-year average and below every merchant-AI challenger (AMD 53x, AVGO 31x, MRVL 41x) — because the market is layering a deceleration scenario on top of structural growth that reverse-DCF shows requires only 12–14% revenue CAGR to justify, a hurdle that hyperscaler capex alone underwrites arithmetically. The moat has demonstrably relocated from CUDA kernel-level software (where ROCm is now an 80–90% substitute) to integrated rack-as-product — NVL72, the 800V Kyber platform, NVLink Fusion, Spectrum-X — where competitors are 12–18 months behind simultaneously, and this meta-moat (the ability to relocate when attacked) is the most important single fact in the thesis. The position works through the 12–30 month Rubin Ultra cycle; from 2028 onward, UALink + merchant CPO + inference-specific architectures create genuine rack-moat retest risk that warrants re-examination at full cycle.
§ 02Sizing rationale
Large (3.5–4.5% NAV) with 40% reserve discipline — not because conviction is soft, but because the entry structure is asymmetric: Section 232, a Q1/Q2 FY27 inventory headline, or an AI Diffusion Rule adverse surprise each represent entry points that improve the risk/reward by 30–50% from current levels. Taking 60% at current forward P/E below 25x for a 60%-operating-margin compounder is justified now; the reserve is deployed tactically on drawdown rather than withheld on thesis uncertainty. Conviction is held at 4, not 5, because the Taiwan tail is genuinely uninsurable (50–70% drawdown in a blockade, per macro.md), the 2027–2028 rack-moat retest is a real uncertainty (not priced in either direction), and the regulatory analyst's 3/5 reflects live two-sided Section 232 variance — none of these, alone, sink the thesis, but together they bound the honest conviction below the 5-grade bar that TSM's more concentrated risk profile earns.
§ 03The 3 things that would make us wrong
- Gross margin compresses below 70% in any single quarter through Q4 FY27 (January 2027) absent a one-time charge — leading indicator: quarterly earnings gross margin line; the financial analyst's terminal-margin assumptions fail at 70% and the entire reverse-DCF validity breaks at sustained sub-72%.
- NVIDIA share of incremental hyperscaler accelerator capex falls below 55% in any 2-quarter rolling window through end of CY2027 — leading indicator: triangulate via AVGO ASIC revenue growth, AMD MI450X shipment disclosures, and hyperscaler capex disclosures; today ~80% merchant share and tracking is achievable.
- AMD MI450X / Helios ships production benchmarks showing >85% of NVL72 utility at <70% of cost by Q4 2026, validated by 2+ hyperscaler procurement announcements — leading indicator: OpenAI's 1 GW initial MI450X deployment benchmark disclosures expected Q4 2026; this is the competitor analyst's specific rack-moat collapse test.
§ 04The catalyst that proves us right
Q3 FY27 earnings print (November 2026) showing clean Blackwell Ultra / early-Rubin gross margin at 74–75% with no inventory writedown — this is the critical confirmation because it simultaneously proves the rack-moat survived its first full competitive cycle (Blackwell Ultra shipping against available MI300X), that pass-through power held margins above the financial analyst's structural floor, and that the inventory build (+112% YoY, $21.4B) was a deliberate pre-build rather than a channel-fill problem. A clean Q3 FY27 print is the single catalyst that retires the three biggest bear arguments in one quarter.
§ 05Add / trim levels
- Add: Deploy 40% reserve on Section 232 tariff-driven drawdown; on a Q1/Q2 FY27 inventory-headline drawdown of 15%+; or on an AI Diffusion Rule adverse-surprise drawdown — all three are entry opportunities on thesis-irrelevant volatility.
- Trim: If gross margin compresses below 70% absent one-time charges; or if NVIDIA share of incremental hyperscaler accelerator capex falls below 55% in any 2-quarter rolling window.
- Cut: Two or more named hyperscalers publicly reduce 2027 NVIDIA GPU procurement by >25% YoY; or inventory growth exceeds 130% YoY for two consecutive quarters with AR DSO crossing 80 days; or Taiwan strait kinetic event (portfolio-level hard stop).
§ 06Pair / hedge
NVDA is a structural long alongside TSM (the underlying wafer + packaging chokepoint). The pair is long-long on AI infrastructure — they move together on Taiwan tail, which is the reason cohort Taiwan-tail exposure is managed at the portfolio level via TXN, ETN, and VRT (three names with low-to-zero Taiwan exposure providing partial structural offset). AVGO is the cleanest partial hedge against NVDA high-end pricing-power compression: every dollar hyperscalers spend on captive ASIC instead of H-series GPUs flows through Broadcom, so the cohort captures the spend regardless of the NVIDIA vs custom-silicon split.
§ 07Why we hold this in a chip-to-grid cohort
NVDA sits at L6/L7 in the chip-to-grid stack as the reference architecture the entire voltage path adapts to — "the rack is the product," and the Kyber 800V platform is literally the architectural decision point that determines how VRT, ETN, Schneider, and Delta size their per-MW content addressability in 2027–2030. Holding NVDA is holding the design-authority node: the entity whose product roadmap determines what every layer of the chip-to-grid stack must build to accommodate.